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From Design To Deployment: How Silicon Lifecycle Management Optimizes The Entire IC Life Span

A new approach is needed for the development, operation, and maintenance of silicon-based systems.

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The beginning of the IC journey gets most of the attention in the semiconductor world – the challenges of design, test and manufacturing. But the reality is the entire lifecycle of a chip needs attention, requiring ways to ensure a chip’s intended and ongoing operation, especially in ever-changing operating environments where chips ultimately reside.

The growing complexity of today’s electronics systems is making quality and reliability increasingly difficult to achieve. This, coupled with little tolerance for performance degradation of any kind and the need to meet functional safety and security requirements, means that a new approach is needed to address how silicon-based systems are developed, operated and maintained.

“Addressing critical chip performance and reliability issues is a multi-billion dollar issue that doesn’t stop at tape out. It requires a new way of looking at the entirety of how an IC is designed, built and used,” said semiconductor industry analyst Rich Wawryzniak from Semico Research.  “Providing access to device data throughout the entire chip life span and enabling on-going ‘in life’ feedback and optimization through specialized analytics will allow a more efficient and effective way to address the semiconductor-related quality and security challenges system companies face in all industries.”

Silicon Lifecycle Management (SLM) is a relatively new process associated with the monitoring, analysis and optimization of semiconductor devices as they are designed, manufactured, tested and deployed in end-user systems.

SLM touches all phases of the semiconductor ecosystem. It aims to collect massive amounts of data about a chip and its operation and use sophisticated analytics to optimize the performance, security and efficiency of the chip and the system in which it is deployed for its entire life. This technology can be used to improve design robustness, reduce design margins, improve power efficiency and validate designs for high reliability applications. While all this produces a substantial improvement in design quality, it is only the start of the SLM journey. True SLM cannot rely on chip data gathered during testing and qualification, it must continue to gather and analyze data for the entire life of the design.

Monitor and analyze
SLM is based on two underlying principles:

  1. Gathering as much useful data about each chip as possible
  2. Analyzing that data throughout its entire lifecycle to gain actionable insights to improve chip and system-related activities

The first principle is achieved by expanding upon the data already available from test and product engineering with deep visibility into each chip’s operation through monitors and sensors that are embedded throughout each chip and measure targeted activities across a wide set of contexts and conditions.

The second SLM platform principle is to apply targeted analytics engines that operate on available chip data to enable optimizations at each stage of the semiconductor lifecycle, starting with design implementation, and progressing through manufacturing, production test, bring-up and culminating with in-field operation.

Combining existing data from chip test and bring-up with new sensor data from chip operation provides the opportunity to develop new insights about the chip and system being analyzed. Predictive analytics can help with maintenance schedules and spot anomalies that may indicate hardware or security compromises. Over the life of any system, operating parameters change. Silicon device performance changes as transistors age. Environmental conditions in the system can cause the operating environment for the chip to drift from its original specifications as well. With a closed-loop system, these conditions can be measured, analyzed and managed in the field.

What are the benefits of Silicon Lifecycle Management?
SLM delivers multiple benefits to the chip designer and the end user of that chip. These include enhanced chip performance, smoother and faster product bring-up and enhanced performance and security over the life of the chip. Specific benefits include:

  • Improved design performance
  • Faster product yield ramp and improved final yield
  • Test time reduction and improved product quality
  • Faster time-to-market for chips and systems
  • Performance, power, reliability and security optimized throughout operational life

Learn more about SLM
This week, Synopsys introduced its Silicon Lifecycle Management platform, the industry’s first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment. To hear more about how the Synopsys SLM platform can bring benefits through the entire lifespan of a chip, attend the Silicon Lifecycle Management track at the  Synopsys Digital Design Technology Symposium to be held virtually on Wednesday, Oct. 14.



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