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How Far Will Copper Interconnects Scale?


As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

Breaking The 2nm Barrier


Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

More Data, More Memory-Scaling Problems


Memories of all types are facing pressures as demands grow for greater capacity, lower cost, faster speeds, and lower power to handle the onslaught of new data being generated daily. Whether it's well-established memory types or novel approaches, continued work is required to keep scaling moving forward as our need for memory grows at an accelerating pace. “Data is the new economy of this ... » read more

System Bits: Oct. 1


Jumping the gap in microchips A quasi-particle that travels along the interface of a metal and dielectric material may be the solution to problems caused by shrinking electronic components, according to an international team of engineers. "Microelectronic chips are ubiquitous today," said Akhlesh Lakhtakia, Evan Pugh University Professor and Charles Godfrey Binder Professor of Engineering S... » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps


Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been ... » read more

Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

Managing Parasitics For Transistor Performance


The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

BEOL Issues At 10nm And 7nm (part 2)


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Uncertainty Grows For 5nm, 3nm


As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena. [getentity id="22586" comment="TSMC"] recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, whic... » read more

BEOL Issues At 10nm And 7nm (Part 1)


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

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