Interconnect Challenges Rising

Resistance and capacitance drive need for new materials and approaches.


Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next.

At 10nm and beyond, IC vendors are determined to scale the two main parts of the finFET structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects may continue to fall further behind the curve.

In fact, the interconnect issues began to emerge at 20nm or so, and the problems are becoming worse at each node. Interconnects—the tiny copper wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.

“RC delay (is) the delay in signal speed through the circuit,” said Rajkumar Jakkaraju, product manager for the Metal Deposition Products Business Unit at Applied Materials, in a recent blog. “RC delay is important because it can become a significant obstacle to continue downward scaling of logic and memory devices that drive the performance of today’s multi-functional, mobile consumer electronic devices.”

In a chip, the average delay due to copper resistivity increased by 7.6% from 45nm to 22nm, according to a recent study from the Georgia Institute of Technology. But the average delay is expected to reach 21.8% from 22nm to 11nm, and by 48% from 11nm to 7nm, according to Georgia Tech.

Over the years, the industry has developed and proposed several solutions to solve the bottleneck in the interconnect. For example, the momentum is building for new materials in the metallization scheme, such as cobalt (Co) and ruthenium (Ru). In addition, a breakthrough technology called air gaps is entering the picture.

But still, the rate of progress and change remains slow amid a slew of challenges in the arena. “That’s the grand challenge,” said Mark Rodder, senior vice president of the Advanced Logic Lab at Samsung. “We really need a breakthrough in the interconnect.”

Needless to say, foundry vendors and their customers need to keep tabs on the progress of the interconnect. So, Semiconductor Engineering has a taken a look at the status of the interconnect, the difficult process steps, and what’s ahead.

What are interconnects?
In a chip, the transistor basically serves as a switch in a device. The transistor is manufactured in the front-end-of-the-line (FEOL) in a wafer fab.

Basically, the transistor is situated on the bottom of the structure. On top of the transistor, there are several levels. A high-end chip might have 8 to 15 levels. These levels consist of a tiny copper wiring scheme, which is connected throughout the chip. This scheme, called the interconnects, are made in the backend-of-the-line () in the fab.

The copper wiring scheme is complex. For example, if the total length of the copper wires was stretched out and measured in Apple’s older-generation A7 application processor, it would amount to an astounding 20 kilometers.

Each interconnect wire is a few atoms thick, while the distance between them is only a few atoms wide. And the wires must be perfectly aligned in the chip. If they are misaligned, the device could take a hit on performance or even fail.

In operation, electrons start at the top of the metal layers and migrate down through the interconnects to the transistor. The flow of electrons through the wires wasn’t a big concern when chips were simpler, but the problems are surfacing at advanced nodes in the BEOL.

“In the BEOL, it’s all about cost, yield, reliability and performance,” said David Fried, chief technology officer at Coventor. “Shrinking dimensions hit those items in a few different ways. First, the patterning scheme to achieve the dense interconnects are driving significant cost/complexity adders and are challenging for yield. Second, shrinking dimensions means the wires have a reduced cross-sectional area, which drives up resistance, thereby impacting performance.”

Basically, copper resistively is increasing for two main reasons—grain boundary scattering and surface effects. In a recent study, researchers from Samsung determined which phenomenon—boundary scattering or surface effects—is the dominant factor in copper resistivity.

Copper resistivity is increasing due to boundary scattering and surface effects.

If researchers could pinpoint the problem, the industry help could solve the RC delay issues. “If grain boundary effects dominate, engineering (the) grain orientations and sizes to minimize this scattering source will reduce resistivity,” said Ganesh Hegde, senior research scientist of Advanced Logic Lab at Samsung, in a recent presentation.

Grain boundary effects aren’t the overriding issue, however. The bad news, according to Samsung, is that surface effects can dominate the resistivity in copper interconnects. In simple terms, copper is running into the laws of physics. “If surface effects (dominate)—especially those arising from simple confinement due to dimensionality reduction—reducing resistivity below that allowed by confinement will not be possible,” Hegde said in a presentation.

The BEOL flow
So what’s the solution to the problem? “The interconnects are becoming a big bottleneck,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “You will need to attack this problem on all fronts. It’s going to take a comprehensive solution of materials, equipment, integration schemes and device layouts. That will dictate what a particular customer uses. And it may not be exactly the same for everybody.”

Others agree. “The interconnect is at an inflection point, and the form it takes will depend on pitch scaling as we move from the 20nm, 10nm and 7nm nodes,” said Mehul Naik, principal member of the technical staff at Applied Materials. “Everybody scales differently. So the solutions to known interconnect high-value problems—such as metal fill, via and line R, capacitance scaling and reliability management—are bucketed based on pitch, and not node. Pitch is the reference point now, not node.”

Meanwhile, in the BEOL flow, there are many process steps. For years, chipmakers have used what’s called a copper dual damascene process, which creates the metal lines and vias. In a simple dual damascene flow, a low-k dielectric material is first deposited on a structure. Based on a carbon doped oxide (SiCOH) material, low-k films are designed to reduce the capacitance and propagation delays in chips.

The idea is to find a low-k film with a low dielectric constant or “k value.” To lower the k values, the films are introduced with porous-like properties. But generally, porous films suffer from poor mechanical properties and are prone to potential damage during the polishing process.

So for years, low-k films have been stuck at the same “k value” at around 2.4 to 2.5. Going forward, chipmakers may lower the “k value” down at incremental steps to 2.2 or so.

But instead of making a quantum leap in low-k scaling, the industry has decided to optimize existing films. “Low-k scaling is focused not so much on reducing film dielectric constant, but developing films with lower process induced damage to effectively get lower integrated capacitance for similar bulk film k,” said Applied’s Mehul.

Still, there are other ways to lower the capacitance. For example, Intel’s 14nm finFET process consists of 9 to 12 metal layers. In the process, Intel implemented air gaps at two layers—MT4 and MT6. Air gaps bring the k-value down to its theoretical limit of 1.0.

Intel’s use of air gaps, in turn, results in a 17% improvement in terms of capacitance, according to Kevin Fischer, backend process integration manager at Intel. Air gaps add cost to the process, but they also have other benefits. “It gives you better performance,” Fischer said.

Intel’s use of air gaps at two metal layers resulted in a 17% improvement in capacitance.

All told, the industry’s emphasis has somewhat changed. Previously, it was attempting to improve the capacitance by finding lower k films. But given the lack of progress on low k, the industry’s focus is now on resistance using new materials and patterning schemes.

Meanwhile, in the next step in the flow, the low-k film is covered with an oxide and a resist. Following that step, vias and trenches are formed using lithography and etch tools. Vias connect one metal layer with another.

For patterning, the industry is using 193nm immersion lithography and multiple patterning. At 7nm and beyond, though, chipmakers would prefer to use extreme ultraviolet (EUV) lithography.

EUV would simplify the process steps, but the question is whether the technology will be ready at 7nm. “The state of EUV technology is much better than a year or two ago,” said , chief executive of D2S.

“The question is whether ‘much better’ is good enough for production,” Fujimura said. “Specifically, people talk about the power source. The other question is the uptime. The question is how long is it going to take to get where EUV is reliable enough that it’s not down half the time.”

Barrier/liner deposition
Once the via/trench is formed in the patterning and etch steps, the structure is lined with a diffusion barrier layer and liner material. The diffusion barrier layers prevent copper atoms from migrating into the dielectric materials.

For years, chipmakers have used the same metallization scheme. A thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier.

At advanced nodes, some will continue to use Ta/TaN. But starting at 20nm, a few others began to replace Ta with Co for the liner. Deposited with chemical vapor deposition (CVD), Co provides a superior wetting layer for copper films.

At 7nm, several chipmakers are evaluating Co and Ru for the liner. In a recent study, IBM and GlobalFoundries compared the two materials for the liner at 7nm.

Ru has better wetting and gap fill properties. “It is clear that the overall process window to obtain copper fill without any sidewall or center voids at 36nm pitch is much larger for TaN/Ru, though a TaN/Co solution is not ruled out by this work,” said Theo Standaert, manager of process integration at IBM, in a presentation.

Ru has some drawbacks, however. “Chemical mechanical polishing for the TaN/Ru barrier system can be quite difficult, since Ru is a noble metal,” Standaert said.

Moving to a new material is easier said than done. “For generations, BEOL engineers have been predicting that the conventional PVD Ta/TaN barrier liner scheme would run out of steam,” Coventor’s Fried said. “And, for years, it hasn’t.”

The traditional flow remains cost effective. The introduction of new materials would provide a number of benefits, but there are also some challenges. “ALD for Co or Ru delivers nearly perfect conformal deposition profiles, and therefore, is seen by many as a potential solution,” Fried said.

“But when I see new work on liner processes, I am typically looking to see the integration benefit, not the intrinsic benefit of the liner film,” Fried said. “The fundamental material will need to be studied. For example, does it meet the reliability criteria? Does it simplify the stack to open up the process window for plating? How much is the cost adder?”

Copper seed
Meanwhile, in the flow, the barrier layer is coated over by a copper seed barrier. And finally, the structure is electroplated with copper and ground flat using CMP.

At advanced nodes, though, the resistivity of copper continues to increase. At the same time, the diffusion barriers are taking up more space, thereby increasing the line resistance.

As a result, researchers are looking at various and futuristic solutions to solve the problem. For example, Lam Research has devised an electroless deposition technique that selectively grows Co materials in vias, followed by conventional copper metallization for the trench.

“We are looking at cobalt as not only a potential barrier/liner candidate, but we can also electroplate cobalt,” Lam’s Hemker said. “Copper will still be there, but you may see cobalt-filled vias.

What’s next?
Beyond 7nm, the industry has been talking about Ru for the liner and manganese-based self-forming barriers. In addition, the industry is also looking at some non-conventional approaches.

“For example, we are working with a university looking at graphene as a diffusion barrier for copper,” Hemker said. “If you put down graphene, you can inhibit copper diffusion. But it’s really hard to do.

“There are also some really interesting possibilities for the backend in terms of organic barriers or organic self-assembled monolayers,” Hemker said. “With self-assembled monolayers, I can engineer the molecules in such a way that they will presumably assemble themselves in the right spot. That’s either a diffusion barrier or a plate-able surface that I can deposit on.”

In the meantime, the industry is looking at new materials to replace copper as the main metal in the interconnect scheme. In fact, at 5nm and beyond, copper may run out of gas. “These problems may be solved by replacing the conventional metals, copper and/or tungsten, by an alternative metal,” said Zsolt Tokei, a program director at Imec.

In the lab, Imec demonstrated 10nm half-pitch Ru interconnects. Co and other metals are also future candidates.

There are other options on the table. For example, instead of traditional scaling, one idea is to go vertical by moving towards advanced stacked die and other 2.5D/3D IC approaches.

“The big question is what applications need (2.5D/3D),” Lam’s Hemker said. “At one point, people were saying everything needs it, which isn’t the case. Some image sensors need it. Mobile needs it from a form-factor sense. And the other place is where it adds to performance, which is the or the Hybrid Memory Cube architectures, where you really need to improve the data flow between the processor and memory. And they’re willing to pay for it because it does add cost.”


Hank Walker says:

From the design viewpoint, one can look at this as the distance that a signal can travel in one clock signal is shrinking as a fraction of the chip. Chuck Seitz (then at Caltech, layer Myricom) wrote about this in “Self-Timed VLSI Systems” in the 1979 Caltech Conference on VLSI. He talked about it as a motivator for self-timed systems, but one can also view it as an impetus for limiting the size of an IP core.

Leave a Reply

(Note: This name will be displayed publicly)