It’s A Materials World

Materials are critical to process technology—even contaminants; challenges continue to escalate at 20nm and beyond.


By Mark LaPedus
At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees.

Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, must have received some input from a (previous) customer: ‘We would really like a more pure material. Can you please eliminate this particular contaminant from this material?’ Somewhere along the way, they ultimately did,” Hendry said.

Unaware that the supplier tweaked the formula, Intel released the material into its process flow. But as it turned out, the contaminant was a necessary part of the process. “That little contaminant was required in order to create the overall crystal reactions in the morphology of that material,” he said. “When it no longer had the contaminant in place, the morphology was entirely different.”

The problem apparently caused an unforeseen disruption, or so-called excursion, in the flow. Eventually, Intel’s fab materials group solved the problem, but not without some headaches along the way. “We eventually figured it out,” he said. “That was six months and I’m surprised my hairline is still where it’s at today.”

Looking back at the episode, Hendry said the problem could have been avoided. “This particular raw material had never been fingerprinted. So my supplier never knew contaminant ‘x’ was even there,” he said. “This is where characterization comes in. You need to know what’s in your material. If you don’t know what’s in your material, there is no way you are going be able to be to control the methodology.”

Saving Moore’s Law
Though perhaps an isolated case at Intel, the event illustrates the growing importance of materials in chip manufacturing. At one time, lithography was the driving force behind chip scaling, but lately, this technology is lagging and threatens the traditional cost-per-transistor curve.

In reality, the shift to new materials is keeping the industry on Moore’s Law, although the transitions have been difficult. Most chipmakers, for example, can still remember the painful migration to low-k dielectrics at 130nm/90nm and high-k/metal-gate at 45nm/28nm.

At 20nm and beyond, the challenges will continue to escalate in materials. “Our fundamental understanding of the materials, and how they interact on the wafer surface and how they interact with each other in the process flow, is relatively immature at this point,” said James O’Neill, senior vice president of electronic materials at ATMI. “There are a number of challenges starting with detection. It is a lot easier to detect defects on the surface of a wafer than it is to detect defects in the materials stream itself.”

To solve those issues at 20nm and beyond, chipmakers may need to increase the steps for process control by as much as 30% to 40%. “There is also a worrisome forecast that the yield of a chip, even at the mature point, may be lower than the previous generation,” warned Wenge Yang, vice president of marketing at Entegris. “The question is how will the industry get lower defects and improve yields?”

This is especially true as the industry moves to new device architectures, such as finFETs, 3D NAND and 2.5D/3D stacked die. And within these architectures, there are a multitude of examples where the industry is moving to new and complex materials.

Strain engineering is one such example. “First, there was the introduction of strain with silicon germanium at 90nm,” said Schubert Chu, product unit head for epitaxial products at Applied Materials. “In the PMOS (epi process), we deposited silicon germanium. Essentially, we tried to incorporate a certain amount of germanium atoms into the silicon. Because there is a lattice mismatch, we imposed a compression on the channel area of the PMOS transistors. That, in turn, increased the mobility.”

Then, there was a sudden change at 32nm. “In addition to the silicon germanium deposited in source-drain, some of our customers have deposited silicon germanium in the channel area for PMOS,” Chu said. “And over the last few nodes, silicon germanium kept improving to a point at where you can see PMOS performance actually surpass the NMOS performance.”

Starting at 22nm, chipmakers are moving towards NMOS epi stressors to boost chip performance. “The dopant incorporated in this case is either carbon or phosphorous,” he said. “Carbon is quite tricky. Carbon is deposited, so it’s in a substitutional silicon set, and not an interstitial spot.”

Today’s finFETs will likely scale to 10nm. Then, at 7nm, finFETs may require III-V materials in the channels to boost chip mobility. In one example, a finFET could have germanium in the PFET and InGaAs in the NFET. Current III-V devices use gold contacts, but gold is incompatible with silicon, meaning the industry must find a new contact material.

The interconnect is another example. In one part of the interconnect structure, tantalum is used to form the liner and tantalum nitride is required for the barrier layer. To solve the resistance-capacitance (RC) delay problems at 14nm and beyond, chipmakers are looking at replacing the tantalum-based liner with either cobalt or ruthenium.

New breakthroughs required
That’s just the tip of the iceberg in the migration towards new materials. The shift in new device structures and materials is putting the onus on the process control tools to solve the problems. “Today, it’s not uncommon for us at advanced nodes to be asked to see small defects on the order of 10nm (on 300mm wafers),” said Brian Trafas, chief marketing officer at KLA-Tencor.

“If I translate this into a Google Map image, it’s like looking at the area between San Francisco and Los Angeles, and inspecting that in an hour and finding basically 100 random scattered dimes in that area,” Trafas said. “That’s essentially what we are doing with our advanced patterning detection systems today. We are sampling roughly 17 trillion pixels in one hour, taking that information and then identifying where those dimes are scattered in that area.”

Detection systems must also determine which dimes landed heads or tails up, and also decipher the given dates for the coins, he said. To stay ahead of the defect curve, process control tools will require more advanced hardware, algorithms and software. On the hardware side, KLA-Tencor is developing brighter sources, finer objectives and faster sensors. “In the last couple years, we’ve invented very high intensity laser pumped light sources. Basically, the intensity is brighter than the sun,” he said.

KLA-Tencor is also embracing design-for-manufacturing (DFM). “We started to incorporate design information. We are working with the designers to understand where the critical patterning issues are,” he added.

From Intel’s perspective, meanwhile, the challenges go back several generations. Five or so years ago, Intel’s metrology and inspection group experienced an inordinate amount of excursion rates, or uncontrolled events, on the line. “With the number of layers and steps, and the excursion rates, you rarely had an operational line,” recalled Intel’s Hendry. “You were in a firefight each day.”