Many Stresses Impact TSVs

To attain optimal performance and reliability, managing mechanical stresses of TSVs in 3D-ICs is critical.


Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs).

Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion.

“If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then that structure will undergo various kinds of thermal treatment,” noted Ric Borges, a senior product marketing manager at Synopsys. “Depending on when the via is fabricated, there could be some additional wafer-level processing to make other devices, such as requiring higher temperatures. But it also could be part of the packaging process itself.”

When that structure gets exposed to temperature the copper will expand at a higher rate than the silicon, so it will be pushing out against the silicon on its sides and will also be pushing up out of the top hole of the via, he explained. “That’s a bit unfortunate because there are many other reasons why copper is an excellent material, but Mother Nature was not very kind and the coefficients of thermal expansion are pretty different. Physically what happens is that as the copper is pushing against the surrounding silicon that will create stresses in the silicon. What then happens is when silicon is exposed to these stress fields, because silicon is a piezoelectric material, any part of the silicon that has stress that is used to fabricate transistors is then subject to do a performance change. This is no different from, for example, the way that people have been engineering strained silicon where they intentionally stress the silicon to improve performance. In this case the stress is unwelcome because it will change the performance in ways that are not intended.”

The electrical current used in devices is proportional to the concentration of carriers (electrons or holes) and mobility (velocity of migration or directed migration under the action of electrical field). Stress affects this mobility, too.

Since first being introduced, everyone now uses engineered stress to increase the mobility of carriers across the gate region, making transistors faster, explained Valeriy Sukharev, principal engineer at Mentor Graphics. “Intentional stress is generated by means of strain engineered sources such as the contact etch stop layer (CESL), stress memorization technique (SMT), epi-silicon-germanium embedded into the source/drain region (Si1-xGex), etc. Stress is good from this point of view, but, ideally we want to have all transistors to be boosted in the same way: you want to introduce the same amount of stress into each transistor and this is a challenge because stress is a large scale phenomenon, strain generated by a localized source can propagate the long distance, and, second, because of the presence in the chip layout of unintentional stress sources, for example, shallow trench isolation (STI), characterized by a variety of planar configurations. If we have two neighbor transistors and we want to introduce stress into an nMOS but not the pMOS..but nevertheless the stress source engineered for nMOS will affect pMOS. However, in general up to now stress effects on 2D structures has been handled with current methods and assessed with the foundry-calibrated circuit simulators.”

Because each layer of a 3D-IC has a different thermal expansion coefficient, warpage and bending, among other things, are a problem as well. “So immediately before any considerations we should accept that we have warpage. Recently people have tried to introduce some new techniques of stacking to minimize this warpage. Why? Because warpage immediately brings stress, and it’s not the worst case because there is a big area of the dies where the stress is almost uniform. But immediately after that we have die etch, die corner interaction of one die edge on another die, and all of these together cause stress,” Sukharev continued.

Keep-Out Zones
Bumps in the underfill add challenges, too. “If we are talking about pure 3D architecture, TSVs are the easiest to deal with because we know it’s enough to introduce ‘keep-out’ zones around TSVs, and the effect on TSVs will be minimal. When it comes to TSV arrays, beyond the keep-out zone, the effect of stress of individual TSVs is small. If we have tens of TSVs, it’s not so small, but it is still nothing in comparison with bumps.”

On the design side, efforts to deal with these issues have mainly addressed TSVs and their impact on device performance using very simple Lame approximations. While not absolutely correct, Sukharev said, if calibration is available, it works pretty well. There are papers available with people coming out with more accurate ways to create models for modeling TSV induced stress — the University of Texas at Austin is one university that is publishing in this area.

Mentor Graphics believes any solution must take into account all known stress sources and is doing research on modeling technology that can convert stress data into the impact of stress on carrier mobility and, thus, variation of the electrical characteristics of transistors.

From his perspective, Borges said analysis is done on the effects in order to simulate the way the stress is generated. “We can simulate the stress fields in the silicon and there will be some preferential direction because silicon is crystalline; there will be some directions where stress behaves a certain way, while in other directions it will behave a different way. Then, when you have multiple TSVs in close proximity interacting with each other, those stress fields can also communicate so things get a little bit complicated.”

Synopsys’ technology simulates all of that and, once the stress simulation is done, he explained, the effect of the stress on the transistor performance and on the drive current is predicted. “All the physics there is pretty well known, and these effects have been measured experimentally on the silicon. What people do is place different arrays of transistors in proximity to TSVs in order to see how their performance is changing. Of course there will be some measurement error, but by measuring enough devices you can statistically come up with contours of performance changes, and those have been very well correlated to the simulations.”

By having the effects characterized and the simulations silicon-validated through these arrays, design teams can define certain areas around the TSV where they will not be placing transistors because there is too much variation.

Performance and reliability risks
Not understanding the extent of the effects can cause a performance hit. If there isn’t a keep out zone characterized, there is a risk of placing transistors that are too close, which will be susceptible to changes from the stress. And electrically, the design will end up being something different from what was intended.

That could affect reliability. “It is possible that as a result of the fabrication the stress levels will become high enough to where you could have mechanical failures of the structure—such as cracks, which will be a big problem for either the immediate or the long-term reliability of the stack,” said Borges. “Also from a reliability point of view, it is important to make sure that there are no stress hotspots, i.e., that the stress levels are all below a safe threshold.”

From the wafer processing perspective, the focus has been on the phenomenon of thermal induced stress in metal full-filled vias. As such, EV Group has been looking at large vias that are completely filled with a metal, according to Antun Peic, business development manager.

“One problem we have observed is the thermal induced stress between the metal filling and its expansion at elevated temperature but also the shrinking when cooling compared to the substrate surrounding material which might be silicon or glass,” said Peic. “One particular problem is integrity of electrical contacts or in extreme cases, the popping out of the whole metal filling from the via.”

This may destroy the electrical contacts as well as the substructures above the via. To avoid this, EV Group believes the best approach is to coat the via with a polymer liner before filling in the metal contacts, which introduces a buffer between the substrate material, where the hole is drilled in, and the metal filling, which is absorbing the stress due to thermal expansion or shrinking.

As the industry travels down technology nodes, Sukharev said new factors become more and more important. “With scaling and the introduction of finFETs, we introduce a lot of additional heat that is generated, and in 3D-IC there is a problem of how to dissipate that heat so new thermal stress can arise because already existing stress sources are not going to disappear. With the thinner dies being used, we should expect more pronounced stress effects. The only way to manage this is to take them seriously into account. Before GDS we need to make the most optimal floorplan in regard to these affects and on each additional design stage this analysis should be repeated and repeated. This will help to avoid a lot of problems that can be figured out when the design is already done and cannot be changed.”

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