Reliability After Planar Silicon

Second of two parts: Why silicon is nearing its end and what comes next.


Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient electrostatic control of the channel at lower operating voltages.

New transistor architectures and new channel materials have not yet been characterized as thoroughly as conventional silicon CMOS, so their reliability and lifetime behavior is not as well understood. Still, at least the outlines of potential reliability concerns are starting to emerge.

Of the proposed new designs, finFETs are the first to approach commercial maturity. In finFETs, the channel is composed of one or more vertical fins, surrounded on three sides by a gate structure. The “trigate” approach, as it is known, gives better electrostatic control. From a reliability perspective, though, it introduces several new concerns.

First, the good news. The fins that make up the channel are typically fully depleted, with little or no doping. Stochastic dopant fluctuations are a significant contributor to the broad distribution of NBTI lifetimes in planar transistors. Reducing dopant density reduces the number of potential defect sites and narrows the range of possible fluctuations. Unfortunately, as IBM’s John Stathis explained in work presented at the 2014 IEEE Electron Device Meeting (IEDM), reducing doping levels also reduces control over the junction profile. Underlapped devices are potentially more vulnerable to hot carrier degradation, in which kinetic energy drives carriers into the dielectric layer. FinFETs also typically have (110) sidewalls, increasing the hot carrier capture cross section.

Finally, the confined fin geometry limits heat dissipation, making self-heating a potential problem for finFET structures. Not only do the electrical properties of silicon change with temperature, but the relationship between temperature and electrical properties changes as transistors shrink. Self-heating reduces carrier mobility and makes all voltage-dependent degradation mechanisms worse. Heating makes reliability prediction more difficult, too: the results of accelerated reliability testing may not correlate with the actual duty cycle of the installed part.

Overall, though, reliability does not appear to be a technology limited for finFETs. Intel’s S. Ramey presented results from the company’s finFET reliability testing at the 2013 IEEE International Reliability Physics Symposium (IRPS). In their work, the negative effects of self-heating and HCI were offset by improvements in NBTI and TDDB. The22 nm tri-gate transistors achieved better reliability than Intel’s planar 32 nm technology.

New channel materials
An even more radical change than finFET architectures, the introduction of high mobility channel materials is likely to upend the transistor manufacturing process. Because most of the vast existing silicon process infrastructure remains relevant, such devices will continue to be built on silicon wafers. However, as discussed at length in an earlier series of articles, the lattice mismatch between silicon, silicon germanium (pMOS), and indium gallium arsenide (nMOS) will require thick buffer layers and possibly new gate stacks.

When the germanium fraction is small, SiGe is relatively easy to incorporate into existing CMOS processes, and indeed it is already making its way into advanced devices. Increasing the germanium fraction increases carrier mobility and leads to more germanium-like device behavior, which is good news for NBTI reliability. As the germanium fraction increases, the Fermi level of the channel goes up. As a result, fewer defects will be energetically favorable at a given bias. (Remember that in pMOS devices, “higher” energies are those which are more negative.) Reducing the thickness of the silicon cap layer — which serves to facilitate formation of an SiO² interfacial layer under the HfO² gate dielectric — increases the Fermi level further. According to reliability studies atIMEC, SiGe devices are likely to have fewer defects, and those which do exist are likely to have a smaller impact on the threshold voltage. While NBTI may limit scaling of silicon pFETs, SiGe pFETs appear to be able to reach the current ITRS reliability targets.

Band structure of SiGe transistor with silicon cap. Increasing the germanium fraction or reducing the silicon cap thickness increases the Fermi level.

Unfortunately, the very characteristics that reduce NBTI are likely to make HCI worse. In highly scaled devices, lateral electric fields are higher, causing a buildup of high energy carriers at the drain. The smaller bandgap of Ge tends to increase hot carrier effects. As Debabrata Maji and co-workers explained, increasing the I^sub/I^d ratio gives carriers more energy to tunnel into the gate dielectric. Reducing the thickness of the silicon cap layer lowers the barrier to tunneling, thereby making HCI worse. Manufacturers will need to balance the NBTI advantages of a thin cap layer against the HCI advantages of a thick one.

While GeFETs demonstrate improved NBTI reliability relative to silicon, HCI reliability is worse. Image via IMEC.

While SiGe appears to be a viable alternative for pMOS transistors, its electron mobility is poor and another channel material will be needed for nMOS transistors. The leading candidate at this time appears to be InGaAs. However, integrating InGaAs with silicon is extremely challenging. The consensus at this year’s Semicon West seemed to be very skeptical of the commercial potential of this material.

While NBTI in pMOS transistors is a concern for silicon devices, nMOS InGaAs transistors face potential PBTI issues. Apart from the change in sign, however, the two failure mechanisms appear to be quite similar. Like NBTI in silicon, PBTI in InGaAs occurs when trapping of carriers causes a threshold voltage shift. And as in silicon, a wide range of capture and emission time constants are seen, leading to a broad distribution of device characteristics. As in silicon, a large fraction of the Vt shift appears to be recoverable when the stress is removed.

However, PBTI behavior in InGaAs is a more severe reliability concern for several reasons. In silicon, carriers are trapped in existing defects, but there are few indications that the applied bias creates new defects. In InGaAs, however, new defects in the interfacial layer can contribute to the Vt shift, and only about 35% shift appears to be recoverable. There are more defects, on average, than in comparably sized silicon devices, and the impact of each defect seems to be greater.

At this time, it’s difficult to say whether the poor PBTI performance of InGaAs is due to the relatively immature state of process integration. While it’s likely that improvement of layer and interface quality will improve the lifetime somewhat, InGaAs integration is very much a work in progress.

Overall, the outlook for pMOS devices is good, with SiGe poised to fill the gap as the limits of silicon are reached. The nMOS picture is not as clear. InGaAs is the most plausible successor to silicon, but both process integration and reliability questions need to be answered first.


Hillol Sarkar says:

Excellent! I will use it for my DFSS article.

Kev says:

If you use asynchronous design techniques and work in the near-threshold region is there really a problem with scaling Silicon?

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