New Challenges For Post-Silicon Channel Materials

Last in a series: Obtaining high-quality materials remains problematic even at smaller wafer sizes. But there are some bright spots.


In order to bring alternative channel materials into the CMOS mainstream, manufacturers need not just individual transistor devices, but fully manufacturable process flows. Work presented at the recent IEEE Electron Device Meeting (Washington, D.C., Dec. 9-11, 2013) showed that substantial work remains to be done on almost all aspects of such a flow.

First and most fundamentally, it is difficult to make integrated circuits without substrates. Most device development work so far has used germanium wafers (for pMOS) or InP wafers with an InGaAs epitaxial layer (for nMOS). That few studies have even attempted to integrate both materials on the same wafer shows how challenging full integration is likely to be. For example, researchers at IBM Zurich used layer transfer techniques to build a hybrid silicon/oxide/SiGe/oxide/InGaAs wafer. Mesa structures were etched into the wafer and used for device fabrication. While preliminary results were good, it is not clear whether such an approach will be manufacturable. Among other challenges, the nMOS and pMOS regions have different elevations relative to the underlying wafer. The depth of focus window for advanced lithography is extremely narrow, so it may not be easy to keep both device types in focus at the same time. Yet, even such a significant lithography issue is irrelevant for the time being. As device quality 300-mm InGaAs wafers are not available, the donor InGaAs layer was grown on a 2-inch (50 mm) InP substrate.

Figure: Process flow for integration of InGaAs n-FETs and SiGe p-FETs on a hybrid wafer. Image courtesy IEEE. 

Simply obtaining high-quality alternative channel materials remains challenging, even at smaller wafer sizes. Germanium MOSFETs had different channel mobility characteristics even when C-V curves and other electrical properties of the starting materials were the same. Research at the University of Tokyo attributed this behavior to the presence of electrically neutral scattering sites, probably oxygen impurities, in the germanium wafers. While it is likely that material quality will improve as market growth provides incentives and resources for suppliers, for the time being it is difficult to tell whether specific results are due to successful process optimizations or to inconsistent starting materials.

In InGaAs transistors, mobility varies substantially with crystalline orientation, with the (111) direction superior to the (100) direction. Irisawa and coworkers started with InGaAs-on-insulator wafers, first selectively etching appropriately-oriented fins into the original substrate, then depositing epitaxial InGaAs on top to make triangular channels. Obviously, any such integration scheme will depend on careful wafer alignment to achieve optimal device performance.

Once device-grade channel materials are achieved, formation of a high quality gate dielectric is the next step. Here, recent results offer reason for optimism. As previously discussed, an initial Al2O3 deposition does not appear to be needed to passivate the InGaAs interface. While a clean surface is essential for successful gate oxide deposition, and atomic layer deposition appears to be an enabling technology for surface preparation, D. Hassan Zadeh and coworkers also obtained good results with La2O3 dielectrics. This material, along with HfO2, offers much a higher dielectric constant than Al2O3, improving ultimate scalability of alternative channel devices.

The most recent work on source and drain contacts for alternative channel materials is also promising. Several different groups have used salicide-like nickel-based contacts with both germanium and InGaAs. In these processes, deposited nickel forms an alloy with the source and drain semiconductor — either germanium or InGaAs — and then excess nickel is etched away. In 2012, workers at IBM achieved a uniform Ni-InGaAs alloy thickness, with an abrupt transition at the substrate. While electrical stability of the alloy is a potential concern at higher processing temperatures, it appears to be due to desorption of III-V semiconductor components, not a phase change, and can be limited with a suitable cap layer. It’s also possible, as Zadeh and coworkers showed, to limit intermixing between the nickel and the semiconductor by forming a NiSi2 contact layer.

While this concludes our special report on alternative channel materials, it of course does not end our ongoing coverage of this topic. We expect to have much more news to report in the months and years ahead. In the meantime, the other articles in this series can be found here: 


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