Germanium wedge-FETs pry away misfit dislocations

Selective etching creates high quality germanium pillars for FinFETs.


Any approach to alternative channel integration must consider the lattice mismatch between silicon and other channel materials. Some schemes, such as IMEC’s selective epitaxy, view the lattice mismatch as an obstacle and look for ways to minimize its effects. This point of view certainly has merit: misfit dislocations do significantly degrade transistor performance. Still, back in 2011 Shu-Han Hsu and colleagues at the National Taiwan University and Taiwan’s National Nano Device Laboratories demonstrated an approach that uses the inevitable defect layer as a means to optimize the overall transistor structure.

The design starts with a germanium layer, deposited on top of a silicon-on-insulator wafer. Due to lattice mismatch, the dislocation density at the silicon/germanium interface can be as high as 109/cm2. Fin formation proceeds by etching all the way down to the wafer’s buried oxide layer, creating isolated pillars of germanium on silicon on oxide. The etch chemistry, a Cl2/HBr-based plasma, removes germanium more quickly than silicon, and defective germanium more quickly than defect-free germanium. Therefore, the etch preferentially removes the defect-rich germanium near the interface. As it proceeds, the area of silicon-germanium contact shrinks and the germanium portion of the fin develops a wedge shape.

Deposition of the Al2O3 gate dielectric and TiN gate metal completes the process, leading to a “gate-all-around” transistor in which a wedge of germanium is surrounded on all sides by the gate structure. Both sub-threshold slope and on/off current ratio improved as the area of contact between the silicon and germanium went down. The best devices demonstrated current ratios as high as 105, and sub-threshold slopes of about 130 mV/decade.

There are obvious challenges in integrating these transistors into a full manufacturing process flow. For example, it is not clear whether it would be feasible to place both germanium wedge pFETs and InGaAs nFETs on the same wafer, due to the need to deposit and then remove large amounts of both materials. On the other hand, by simply etching away the defect-rich interfacial layer, this approach avoids a whole stack of strain-relief buffer layers.


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