Will 7nm And 5nm Really Happen?

First of two parts: New materials and transistors could extend Moore’s Law to 1.5nm or beyond, but there are a lot of problems ahead and a lot of unanswered questions.


As leading-edge chipmakers continue to ramp up their 28nm and 20nm devices, vendors are also updating their future technology roadmaps. In fact, IC makers are talking about their new shipment schedules for 10nm. And GlobalFoundries, Intel, Samsung and TSMC are narrowing down the options for 7nm, 5nm and beyond.

There is a high probability that IC makers can scale to 10nm, but vendors face a multitude of challenges at 7nm and beyond. The big question is whether the 7nm node will ever happen. And is 5nm even possible? The 3nm node is too far out in the future and is still up in the air.

If the industry moves beyond 10nm, it won’t be a straightforward process of simply scaling the gate length, as in previous nodes. The migration to 7nm itself requires a monumental and expensive shift towards new transistor architectures, channel materials and interconnects. It also involves the development of new fab tools and materials, which are either immature or don’t exist today.

Technically, it’s possible to make 7nm and 5nm chips in R&D. One challenge is to design and manufacture devices that meet the cost and power requirements for systems. Another challenge is to make the right technology choices, as the roadmap for the various options remains in flux.

Indeed, in the previous roadmaps among many entities, the leading transistor candidate has been the high-mobility or III-V finFET at 7nm, followed by a next-generation transistor type at 5nm.

Now, the options are all over the map. For example, according to Imec’s latest roadmap, III-V finFETs may get pushed out to 5nm, although they could still appear at 7nm. And a next-generation transistor could arrive as early as 7nm, according to Imec.

At 7nm, there are three main transistor candidates—gate-all-around FETs; quantum well finFETs; and SOI finFETs, according to Imec. Gate-all-around is the favorite, but it’s still too early to declare a winner. Meanwhile, germanium (Ge), not the exotic III-Vs, is the leading option for the channel materials at 7nm.

As before, the industry is searching for technologies that are cost-effective, production-worthy, and which can scale. What’s changed is that chipmakers want to accelerate the development of select technologies, and introduce them much earlier in the flow, to get a jump on the competition.

In any case, Imec’s roadmap provides a glimpse into the future. In its CMOS program, the R&D organization collaborates with several member companies, such as GlobalFoundries, Intel, Samsung and TSMC. Imec helps conduct the R&D and narrows down the options for its members. Then, it’s up to Imec’s partners to make the final decisions.

Based on the roadmaps from Imec and its members, the industry is targeting 7nm in the 2018 timeframe. And not surprisingly, the group also hopes to dispel the notion that chip scaling, and Moore’s Law, is on its last legs. “The question is not whether 7nm will happen or not,” said Luc Van den hove, president and chief executive of Imec. “7nm will happen. The question is whether it will happen with a little bit of a delay or not. So, the question is not whether scaling will go on. The question is whether it will slow down.”

Imec and its partners are also weighing the options for 5nm and beyond. “Of course, the uncertainty increases (beyond 7nm),” Van den hove said. “There are still so many options in the pipeline.”

Beyond 10nm, IC design and manufacturing costs will be enormous. Only a few chipmakers have the technology know-how and resources to design and manufacture these devices. And so, the industry must collaborate more than ever before, said E.S. Jung, executive vice president of the semiconductor R&D center at Samsung Electronics. “We are doing three nodes at the same time in our R&D center. My target is to approach 1.5nm,” Jung said. “How can we make it happen? We need tools, materials and open innovation. Also, we cannot do it all by ourselves.”

The options
In the near term, the leading-edge chip roadmap looks clear. Chips based on today’s finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture.

One of the leading contenders for 7nm has been the high-mobility finFET, which is a finFET with III-V materials in the channels. The III-V finFET would supposedly consist of Ge for PFET and indium-gallium-arsenide (InGaAs) for NFET.

“Germanium is making good progress,” said An Steegen, senior vice president of process technology at Imec. “III-V is tricky. It still needs more work.”

In fact, III-V technology is challenging and could get pushed out to 5nm. “Ge and III-V channels are still hot contenders at 7nm,” added Aaron Thean, director of the logic program at Imec. “However, the narrow bandgap of these materials are presenting problems for low-leakage transistors. The outlook for these (III-V) materials is moving from 7nm to likely 5nm. This does not preclude the use of these materials in the source/drain in the nearer term.”

So with the possible delay of the III-V finFET, what’s next for 7nm? Imec is weighing several transistor options, namely gate-all-around, quantum well finFETs, and SOI finFETs. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. “At a certain point in your process (for gate-all-around), you are going to undercut that fin. Then you come in with a dielectric in the gate and you basically fill in underneath the channel, which is now a nanowire,” Imec’s Steegan said.

“There is, of course, SOI,” she said. “You can also have an effective quantum well. (In this structure), you build in an effective energy area to basically shut down the leakage path.”

For the channel materials at 7nm, Imec has narrowed down the options to two choices—an 80% composition of Ge for PFET; or a 25% to 50% mix of Ge for PFET and 0 to 25% of Ge for NFET with strain relaxed buffers. “The perfect candidate, of course, is germanium,” she said. “The silicon devices are operating at 0.8 and 0.75 volts. But the germanium devices are operating at 0.5 volts. So you have exactly what you want in performance as well as the electrostatic behavior. But, of course, you have lower Vdd, so you save power.”

Following 7nm, the industry is looking at several transistor options for 5nm—gate-all-around; quantum well; SOI finFETs; III-V finFETs; and vertical nanowires. “We are looking at all of the aspects for vertical nanowires,” she said. “We are exploring how we grow the channels. And do we use channel last or first integration schemes?”

The challenges
The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec’s CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source.

Imec has a window into the progress of EUV. It is a development partner with ASML and serves as a beta-site for ASML’s EUV tools. “The progress is there (with the EUV source). I think it’s on the order of 35 wafers per hour now,” Imec’s Van den hove said. “So for 7nm, I am pretty confident EUV will be there at that time.”

By 7nm, the industry may require both EUV and multiple patterning. “At 7nm, we need layers down to a pitch of about 21nm,” said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. “That’s already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it’s going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.”

But if EUV misses the window, the industry can still move forward with 193nm immersion and multiple patterning. “If EUV is not ready, the fins (can be done) using spacer patterning,” said Reza Arghavani, a fellow at Lam Research. “Obviously, spacer patterning requires fin deposition and etch. If you have to do it twice, you have to go through immersion lithography twice too. But when you do it twice, the cost goes up. But you might have to do it three times. The cost goes up again. That’s the issue.”

Patterning is only one piece of the puzzle. “By the time you get to 7nm, you’ve already had 22nm, 14/16nm, and 10nm on finFETs,” Applied’s Brand said. “So that’s three generations on finFET technology. But as you keep scaling down the finFET, you get the same kind of problem of a gate-coupling to the channel as you had on planar devices.”

So at 7nm, the industry may require a new transistor technology that reduces the gate length and maintains good performance. “Gate-all-around is the most effective (solution),” Brand said. “I would place my bet in that direction.”

Gate-all-around is not as radical as many believe. “It’s quite practical. You could even think of gate-all-around as an evolution to the finFET. It’s just increasing the number of sides where the gate is wrapped around the channel,” he said. “Now, does that happen at 7nm exactly? It will be at 7nm or 5nm, based on where the industry is going. The exact node depends on how aggressive companies are in reducing the gate length.”

Still, gate-all-around requires a complex nanowire structure, which has not been demonstrated with well controlled dimensions. “There are a number of challenges. One of the big ones is contact resistance,” he said.

What about cost? “The additional cost of the finFET (from Intel at 22nm) was only about 5% on the overall process flow, (as compared to planar),” he said. “So you can bring in a disruptive new technology with only changing a few things in the process. And gate-all-around can be like that if it’s done in a horizontal layout. If you do a horizontal layout with gate-all-around, you can still have many of the same steps in the process. You, of course, will add some complexity such as epi, selective removal and ALD.”

Still, there is another school of thought. For decades, the industry has designed and made chips using planar transistors. Now, the IC design and manufacturing communities must adapt to finFETs. And at 7nm, the transistor could see a more radical change, which could cause another design disruption.

For that reason, some believe the industry should extend the finFET. “Gate-all-around and other structural changes to transistors are options, but I strongly believe the extension of finFET technology is the lead approach,” Lam’s Arghavani said. “I believe the industry will extend finFET technology as far as it can. It took significant changes in design and process development to transition to finFET from planar transistors. So the industry would not switch to another transistor structure unless absolutely necessary.”

Beyond 10nm, there are several ways to extend finFETs. “Transitioning the fin to III-V, Ge or make the fins taller are natural extensions of finFET technology, but not all the elements of this technology, such as deposition of III-V, is ready yet,” he said. “There is still a lot of learning (with III-V), but I’m pretty sure we will get there. But the question is will we get there by 7nm? That I doubt.”

Clearly, chipmakers are moving full speed ahead towards 7nm and 5nm. TSMC, for one, hopes to show 7nm test chips by the end of 2014. TSMC and others are taking a hard look at gate-all-around, but nothing is set in stone. Placing the wrong bet could be a disaster. “So, we are still weighing all of the options,” said Jack Sun, vice president of research and development and chief technology officer of TSMC.

To view part 2 of this series, click here.

Related stories:
Billions And Billions Invested

The Search For The Next Transistor

New Challenges For Post-Silicon Channel Materials

What’s After CMOS?

How Much Will That Chip Cost?


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Isobel_Riel says:

IC manufacturers continue to announce new generations, 45 nanometer, 32 nanometer, 22 nanometer, and coming soon, 14 nanometer, though in fact we have been stuck at 64 nanometer for quite some time. There have been process improvements, but these are incremental improvements. The line pitch remains 64 nanometers. We cannot actually build circuits smaller than we could eight years ago. That these are improvements is no lie, but to label them by a size is a lie. If they had said “second generation 64 nanometer” instead of “45 nanometer”, if they had said “third generation 64 nanometer instead of “32 nanometer”, then they would have been speaking truth, or at least speaking hype rather than lies.

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