Best Practices and HPC Strategies for Ansys Mechanical


Mechanical engineers face growing complexity in structural simulations. Modeling intricate geometries, capturing nonlinear material behaviors, and ensuring accurate boundary conditions often push traditional computing resources to their limits. These challenges can lead to longer solve times, convergence issues, and difficulties interpreting results — all of which slow innovation and impact p... » read more

Network Security For AI/HPC: From MACsec/IPsec Towards Ultra Ethernet


The modern world is increasingly a digital one that encompasses the realm of electronic devices, the internet, and online platforms. This world is constantly evolving, driven by technological advancements and shaped by how humans interact with digital technologies. The key element of a digital world is information that needs to be collected, stored and processed in vast quantities. For many ... » read more

UEC-CBFC: Credit-Based Flow Control For Next-Gen Ethernet In AI And HPC


For ages, Ethernet has been the backbone of networking — starting from simple web browsing to cloud computing, data centers, automobiles, and more. Ethernet has enabled countless innovations, and now, it's expanding to meet the demands of AI and HPC. As the world shifts toward these new technologies, new challenges are emerging. These include increased scale, higher bandwidth density, mult... » read more

Best Practices to Optimize Infrastructure for Simulations


Our Best Practices Guide equips you with expert strategies for leveraging high-performance computing (HPC) to maximize Ansys workload efficiency and overcome common challenges. As simulation complexity increases, a robust computing infrastructure is essential for rapid and large-scale modeling. Modern HPC systems provide: High-core-count CPUs for superior memory and compute perfo... » read more

UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC


As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic. In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As ... » read more

Mixed-Criticality SW Architectures for Centralized HPC Platforms in Software-Defined Vehicles (Daimler, TU Munich)


A new technical paper titled "Towards Mixed-Criticality Software Architectures for Centralized HPC Platforms in Software-Defined Vehicles: A Systematic Literature Review" was published by researchers at Daimler Truck AG and Technical University of Munich. Abstract "Centralized electrical/electronic architectures and High-Performance Computers (HPCs) are redefining automotive software develo... » read more

The Best DRAMs For Artificial Intelligence


Artificial intelligence (AI) involves intense computing and tons of data. The computing may be performed by CPUs, GPUs, or dedicated accelerators, and while the data travels through DRAM on its way to the processor, the best DRAM type for this purpose depends on the type of system that is performing the training or inference. The memory challenge facing engineering teams today is how to keep... » read more

Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)


A new technical paper titled "Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design" was published by researchers at Peter Grünberg Institute and Jülich Supercomputing Centre. Abstract "Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention s... » read more

High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI


By Lakshmi Jain and Wei-Yu Ma The AI and HPC industries are rapidly shifting toward chiplet-based designs to achieve unprecedented levels of performance, as traditional monolithic system-on-chip (SoC) architectures face scaling limitations. This transition is fueled by the rise of heterogeneous integration, which is driving innovation across the semiconductor sector. However, this advancemen... » read more

Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors


A new technical paper titled "Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor" was published by researchers at Jülich Supercomputing Centre and KTH Royal Institute of Technology. Abstract "Memory prefetching is a well-known technique for mitigating the negative impact of memory access latencies on memory bandwidth. This problem has become more p... » read more

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