The Opportunities And Challenges Of FOPLP Technology

Artificial intelligence (AI) has emerged as a major catalyst for innovation and advancement. The growing demand for AI computing power is driving heterogeneous integration toward larger packaging sizes, sparking increased interest in Fan-out Panel Level Package (FOPLP) technology. This article explores ASE’s practices and developments in this area, delving into the technical intricacies and emerging trends shaping the future of the industry.

Advanced packaging for AI/HPC

The advanced packaging architecture designed for AI and high-performance computing (HPC) applications involves positioning memory in close proximity to AI processors, such as GPUs and AI ASICs, on a common interposer, rather than placing them separately on a printed circuit board (PCB). This configuration reduces the distance between the memory and the ASICs, enabling faster speeds, increased bandwidth, and greater capacity, ultimately boosting overall computing power.

As the demand for computing power grows, interposers need to accommodate more chips in a side-by-side configuration, driving an increase in size. Currently, ASE has achieved interposers with three times the reticle size, but future demands are trending toward even larger dimensions, such as 3.5x, 4.5x, and 5.5x. A 5.5x reticle size interposer is approximately 60mm x 70mm, exceeding the size of today’s mass-produced packaging substrates.

The advantages of panel-level packaging process

The benefits of panel processing may seem limited when producing small-sized interposers. However, the advantages become more pronounced as interposer sizes increase. In particular, the utilization of circular substrates in wafer processing decreases as the sizes of the interposers grow, because edge dies occupy more space, leading to greater material waste after singulation. For example, a 12-inch (300mm) wafer can accommodate only nine interposers sized at 5.5x reticle size. In contrast, a 300mm panel can fit 16 interposers of the same size. This translates to significant efficiency gains (1.78 times) when transitioning from wafer to panel. In summary, for large interposers (>3x reticle size) used in chip integration, the panel process clearly outperforms the wafer process.

Fan-out packaging technology for AI/HPC

Currently, advanced packaging technologies for integrating AI chiplets, such as GPUs and memory, primarily consist of two platforms: Si interposer and organic interposer. The method of placing chips on a Si interposer for functional integration is known as 2.5D packaging. In contrast, the organic interposer utilizes a redistribution layer (RDL) for functional integration, referred to as FOCoS (Fan Out Chip-on-Substrate) packaging. If a bridging structure is incorporated within the RDL interposer, it is termed FOCoS-Bridge.

FOCoS: Chip first vs chip last

There are two main approaches for FOCoS: Chip First and Chip Last. The Chip First method is primarily used for packaging and integrating small chips. The process begins with placing the chips on a carrier, followed by molding and then adding the redistribution layer (RDL). Generally, it is not recommended to integrate too many chips using the Chip First process, typically limiting it to around two to three chips. Additionally, the entire interposer’s reticle size is not advised to be too large (typically <1x reticle size), and it usually involves about 2 to 3 layers of RDL.

Currently, the integration of ASICs and high-bandwidth memory (HBM) in HPC and AI applications is primarily accomplished using Chip Last solutions. This involves preparing the RDL interposer on a carrier and then placing the chips onto the RDL interposer for connection. Generally, the reticle size of Chip Last RDL interposers is relatively large (>1x reticle size), and in the future, it may require up to 9 layers of RDL, including at least 7 layers of fine-lines having line width/line spacing (L/S) that can achieve 2/2μm.

Key challenges of FOCoS

With advancements in semiconductor technology, the μBump pitch of the top die ASIC has gradually decreased from 55μm to 40μm, and it could shrink further to 25–30μm in the future. This decrease presents increasing challenges in the packaging process. Furthermore, to meet the growing demand for AI computing power, HBM integration has evolved from four-layer to eight-layer and even twelve-layer memory stacks. The number of HBMs around the ASIC on the interposer is also increasing, with current trends favoring four or eight HBMs, and future plans aiming for twelve or even twenty. As more chiplets are integrated, the interposers are becoming larger.

Typically, an RDL interposer requires two layers of 2/2μm fine lines for communication between the ASIC and HBM2/2E, while HBM3/3E needs four layers of 2/2μm fine lines, and HBM4/4E may require an 8-layer RDL with 6 layers of fine lines. In some designs, 8 layers of 2/2μm fine lines may be necessary to effectively integrate these memory components with advanced ASIC chips for optimal communication.

Technology trends of FOCoS-Bridge

FOCoS-Bridge technology utilizes Silicon Bridge to provide fine lines (L/S<0.5/0.5μm) for interconnecting chips. Therefore, the routing density requirement of RDL on FOCoS-Bridge interposer is lower than that of FOCoS interposer; the L/S only needs to reach at least 5/5 μm. The Silicon Bridge is typically fabricated in a foundry of TSMC, UMC, or GlobalFoundries.

To address the increasing complexity of chip integration, FOCoS-Bridge technology enhances design flexibility by utilizing a Silicon Bridge for high routing density interconnections between chips while providing wide-pitch RDL layers on the interposer for power and signal delivery. It can also integrate additional components, like independent Integrated Passive Devices (IPDs), beneath the ASIC chip to enhance power integrity (PI) and signal integrity (SI).

Key challenges of FOCoS-Bridge

FOCoS-Bridge technology requires many tall copper pillars, as shown in the drawing below, around the Bridge Dies for vertical connections. The spacing between these pillars has been reduced from 150 μm to about 130 μm to meet the growing demand for more vertical connections.

As FOCoS-Bridge technology becomes more complex, future Bridge Dies will need to incorporate Through-Silicon Vias (TSVs), similar to those used in the Si Interposer of 2.5D packaging, to provide a more efficient vertical path for power delivery. Moreover, as HPC power delivery requirements become more intricate, it is essential to integrate Deep Trench Capacitors (DTCs) into the FOCoS-Bridge Interposer to support better PI/SI signal communication.

Fan-out PLP development

ASE is developing an automated production line using a 310×310 mm panel. While larger panel sizes can be more cost-effective, they also pose greater manufacturing challenges. To address this, ASE is starting with a smaller panel to develop the FOPLP process for advanced AI and HPC packaging, with plans to scale up to a 600×600 mm panel.

Panel process challenges of FOCoS-Bridge TV

The test vehicle (TV) shown in the figure below is manufactured on a 300×300 mm panel. Although the process is similar to the previously introduced FOCoS-Bridge technology, there are significant technical differences due to the transition from wafer (circular) process to panel (square) process. For example, the typical spin coating used in wafer processing cannot be directly applied to panel processing; instead, it needs to be changed to slit coating, and the materials also need to be adjusted. In addition, the interposer for integrating AI chiplets is typically larger than a single exposure field, requiring multi-reticle stitching in current wafer lithography process. Therefore, maskless exposure technologies like Laser Direct Imaging (LDI) prevail, as they significantly enhance production efficiency and offer flexible compensation through software settings, without the limitations of masks.

The main manufacturing steps of the FOCoS-Bridge TV are as follows:

(a) After forming Tall Pillars on the panel, the Bridge Die is placed, followed by molding and grinding. Precise placement of the Bridge Die is critical; otherwise, the via holes of the first dielectric layer, PI passivation (formed after grinding), will be difficult to align precisely with the Cu Studs on the Bridge Die. As the Micro Bump Pitch of the Top Die has been scaled down to about 35μm to 40μm, the Cu Studs may be formed at just 20μm, while the PI vias may be as small as 10 to 15μm.

(b) Multiple layers of RDL and μBump Pads are formed on the molded product to complete fan-out interposer construction. Key technical challenges include achieving uniformity in slit coating, accuracy in lithography, and controlling plating thickness during electroplating.

(c) The AI chiplets are then attached to the interposer which is roughly three times the size of a reticle, close to 50mm x 50mm. Finally, after applying underfill and molding, the carrier is removed and controlled-collapse chip connection (C4) bumps are formed on the backside of the interposer.

Future outlook

Given the complexity of these challenges, ASE recognizes that achieving FOPLP independently is challenging. Collaboration with equipment manufacturers, material suppliers, and automation providers is essential. In this fast-evolving landscape, each advancement in semiconductor packaging technology unlocks new possibilities. Together, we can leverage FOPLP to shape the next remarkable chapter in the semiconductor industry.