Hybrid bonding already works in production, but finer-pitch die-to-wafer integration must preserve fab-level surface and alignment control at back-end volumes and costs.
Key Takeaways:
Hybrid bonding has already crossed the threshold from research into production, but that achievement is less complete than it first appears.
Image sensors and other wafer-to-wafer applications have shown that prepared copper and dielectric surfaces can be joined reliably at scale. The more difficult transition involves finer pitches, die-level processing, and products that combine logic, memory, and other functions whose materials, dimensions, and thermal limits were never designed to be identical.
A recent Semiconductor Engineering article, How To Build Billions of Bumps, examined the extraordinary interconnect populations that become possible when hybrid-bonding pads are formed across a wafer in parallel, provided the upstream processes remain extremely uniform and test compensates for the impracticality of inspecting every completed connection. Fine-pitch die-to-wafer bonding inherits all of those requirements, but it adds a different manufacturing problem once each die is screened, handled, aligned, and placed as a separate mechanical object.
The bond itself forms near the end of that multi-step progression, but its yield reflects nearly everything that happened before the two surfaces touched. Copper recess, dielectric topography, particle contamination, film stress, wafer shape, die thickness, temporary bonding, cleaning, activation, and placement all contribute to the final error budget. Each process can appear capable in isolation, but their combined variation may not leave a process window in which the surfaces can bond repeatedly.
That accumulation of small deviations is what separates a working process from a high-volume one. The bonding mechanism may be established, but production depends on whether the complete process can return to the same physical condition thousands of times without allowing one variable to consume the margin reserved for another.
“Once you figure out how to do it, then it’s about holding almost everything as stable as possible,” said Erik Edelberg, corporate vice president and general manager for Dielectrics Deposition at Lam Research. “HVM is all about high volume, wafer-to-wafer consistency, and across-wafer consistency.”
Fig. 1: Cross-sectional electron micrograph of a 1 µm-pitch hybrid-bonding interface. Source: CEA-Leti
Volume is not one condition
The phrase “high-volume manufacturing” can obscure important differences among hybrid-bonding flows. Wafer-to-wafer bonding is just one of many processes in parallel. It benefits from the regular positioning of two patterned wafers, but the yield of the combined structure depends on the quality and compatibility of both. Die-to-wafer bonding trades that parallelism for flexibility, and collective die-to-wafer approaches attempt to recover some of it by transferring multiple dies together. But the collective advantage becomes more difficult to preserve as pad size shrinks because the pitch must tolerate the placement variation of the collective process.
The result is that fine pitch cannot be defined only by the smallest connection demonstrated in a laboratory. A commercially useful pitch delivers enough routing, power, or performance benefit to justify the manufacturing controls it requires. A 6 µm logic-to-memory interface may create substantial system value even while 1 µm bonding remains a longer-term process and materials target. That difference between roadmap scaling and production value shapes where adoption is likely to begin.
“The go-to minimum pitch now is about six microns,” said Mike Kelly, vice president of chiplets and FCBGA integration at Amkor. “There are roadmaps out there going all the way to one-micron pitch, but six microns is likely to remain the commercially viable spot for quite a while.”
The manufacturing challenge does not rise uniformly with every reduction in pitch. A placement offset or local surface distortion that reduces pad overlap at 6 µm may eliminate it entirely when the pad itself is only a fraction of a micron wide. Processes that once appeared loosely coupled begin competing for the same shrinking tolerance, and improvements in bonder accuracy cannot recover geometry that has already been altered by stress or warpage.
The price of die selection
Die-to-wafer bonding is attractive because it prevents one poor region on a source wafer from condemning an otherwise valuable stack. Manufacturers can test dies before bonding, select the yielding ones, and place different die types only where they are needed. But the yield advantage comes at the cost of parallelism, because die-to-wafer assembly must pick, transport, orient, inspect, align, and place each die after it has been singulated and exposed to a handling environment that differs from the original wafer process. Individual placement sacrifices speed, but it provides a level of control that collective approaches may struggle to maintain as pad dimensions approach the placement error of the tool.
“Die-to-wafer is a challenging yet promising approach because, even if we are having low throughput when we are going for individual placement of the dies, we are sure that we are controlling the alignment,” said Melissa Najem, research engineer at CEA-Leti. “For fine pitch, the most challenging factor is the alignment, so once we are working on the alignment, we can have better electrical yield.”
Known-good die selection changes the economics, but it doesn’t guarantee a successful final interface. Pre-bond test can establish that the die functions before assembly, but it cannot certify a connection that has not yet been formed. Post-bond electrical test remains the most direct evidence that the interface works, although by that point the selected die, the base wafer, and the bonding operation have already contributed their cost. Rejecting too aggressively wastes acceptable die, but using marginal material places more accumulated value at risk. High-volume die-to-wafer bonding will require enough surface, shape, electrical, and process-history data to make that decision rational before the most expensive irreversible steps.
“We can perform some known-good-die procedure in order to see which dies are really good to be bonded,” added Najem. “And by this, we can increase the yield of our production.”
But throughput cannot be raised simply by moving the placement stage faster. Vision, alignment, settling, surface exposure time, contact initiation, and bond-wave behavior must all remain within the qualified range as cycle time falls. A faster bonder that widens the placement distribution or exposes activated surfaces for inconsistent periods may increase nominal units per hour while reducing the number of usable assemblies that leave the line.
Clean enough without building another fab
Particle control illustrates why transferring hybrid bonding from a front-end fab to an OSAT is not a straightforward equipment move. A leading-edge fab already operates within an infrastructure designed to limit airborne contamination, control chemical purity, and manage wafer movement through highly enclosed systems. An assembly facility is built around different products, cost structures, and process histories. Reproducing an entire front-end cleanroom around back-end bonding would erase much of the economic benefit of moving the process there.
Hybrid bonding also gives particles unusual leverage. The dielectric surfaces must come into intimate contact across the bond area, and there is no compliant solder structure or organic underfill at the interface to absorb a local obstruction. The problem becomes especially acute as hybrid bonding moves into assembly environments. The practical response is increasingly to create localized zones of extreme cleanliness inside or around the bonding cluster rather than trying to convert the entire OSAT into a front-end fab.
“It’s super-sensitive to any kind of particulate contamination because essentially it’s a glass-to-glass interface,” said Amkor’s Kelly. “There are no organics for compliance. It only takes one nanosized particle, and you basically lift the glass off, and you’ve messed up a whole bunch of units on the wafer.”
Local cleanliness must extend beyond the instant when the surfaces meet, as well. Dies pass through singulation, temporary bonding, cleaning, metrology, transport, and alignment before bonding, and each step can add particles or expose a prepared surface to new contaminants. The usable lifetime of an activated surface also makes queue time part of the process window, because a surface that was qualified immediately after preparation may no longer be in the same chemical state after an uncontrolled delay.
Cleaning cannot be treated simply as the application of greater mechanical force, either. The smaller the particle, the more difficult it is to remove without damaging the copper, dielectric, or underlying structures, and the chemistry must distinguish between the contaminant and the surface that’s activated for bonding. Surface condition is therefore inseparable from the rest of the process integration.
“It is a difficult challenge in the world of chemistry. That has always been the case, because the smaller you get, the stickier you are,” said Sanjiv Bhatt, senior director of global marketing and business development for Mitsubishi Chemical Group’s Semiconductor Business. “The smaller it is, the more exponential is the adhesion. You are trying to get in between that particle and whatever it’s sitting on. You can apply mechanical or acoustic forces to move it, but the key is that if you can put something that actually weakens the interface, now we have removed it, and that depends on what kind of molecule you have.”
CMP provides one example of that coupling. The dielectric surface must be sufficiently flat and smooth to establish the initial bond, but the copper pads cannot simply be polished to an idealized room-temperature plane without considering what happens during annealing. Copper expands more than the surrounding material, so a controlled recess allows the pads to fuse as temperature rises. Too much recess can leave an incomplete electrical connection, and too little can drive excessive deformation.
“Surface topography is really important, as is the surface chemistry, because you have to bond these two surfaces together, and there’s usually an activated state of those surfaces,” said Lam Research’s Edelberg. “Material stress is also a really interesting challenge because it plays into the whole shape and distortion of the dies. Then, of course, there’s cleanliness, because all of that comes together at the bond interface.”
Alignment begins before placement
The next constraint appears at the bonder, but it doesn’t begin there. Placement equipment aligns the features it can measure, while the physical locations of those features have already been altered by film stress, wafer bow, die thickness, and the thermal cycles used to build the structure.
Traditional warpage specifications describe only part of that condition. A wafer can remain inside an overall bow limit while containing local topography or higher-order distortions that consume the overlap margin in selected regions. The relevant geometry spans several length scales — from low-order bow to local slope and die-level deformations introduced by bonding, CMP, redistribution layers, and material mismatches — rather than one flatness number.
“We have to ask instead of, ‘Is this flat,’ which shape components really matter to the yield, reliability, bonding, alignment, and final system performance?” said Adam Cheung, vice president of business development at Wooptix. “Flatness must evolve into a surface geometry budget. From the geometry budget, we can decompose it into substrates, into package shapes, and how they contribute to the entire yield of a complete chip system.”
The distinction becomes more important once a die is separated from its source wafer. Singulation releases stress, temporary bonding constrains the die again, and thinning changes its stiffness. Consequently, the geometry presented to the bonder may differ from the geometry measured earlier in the process. The die can be positioned correctly at one reference point while its outer pads remain displaced by scaling, rotation, or nonlinear distortion.
Intel Foundry presented one example of how those variables interact at a recent iMAPS conference. In the test vehicles described by Yi Shi, increasing chiplet thickness reduced linear-scaling distortion, while increasing chiplet warpage increased it. The work also showed that changing the bonder nozzle geometry altered the directional distortion pattern, and a calibrated finite-element model reproduced the experimental behavior closely enough to explore bond force, vacuum timing, and other conditions without fabricating a separate test vehicle for every combination.
That modeling approach changes how manufacturers can think about alignment control. Overlay data collected after bonding can be separated into rigid placement error, linear scaling, and higher-order residuals, then fed back into a mechanical model of the die and bonder. The residual pattern may be more useful than a single pass/fail number because it can identify a process condition beginning to shift before that shift becomes large enough to cause widespread opens. A faster production bonder will still need stable accuracy across repeated die placements, but it also will need incoming material whose local geometry remains within the range the tool can correct.
The temporary stack leaves a permanent mark
Much of that incoming geometry is established while the wafer is attached to a temporary carrier. Thinned silicon, molded wafers, and partially built packages often lack the mechanical stability to move through backside processing, RDL formation, or additional deposition on their own. The carrier and temporary bonding material become the mechanical reference for those operations, even though neither remains in the finished device.
Carrier choice also affects how the workpiece responds as the temperature rises and falls. Glass, silicon, and other carrier materials offer different stiffness and CTE behavior, while the temporary adhesive determines how much of that movement is transferred into the wafer. Adhesion must remain strong enough to prevent slipping or delamination, but the layer also needs sufficient compliance so it does not impose excessive stress on its own.
“If the CTE doesn’t match, or isn’t close enough for the carrier wafer and your package, you’re going to end up with a lot of warpage,” said Hamed Derami, technology strategist for advanced packaging at Brewer Science. “Warpage in each step is going to affect the next downstream step.”
The material requirements also change with the flow, because a formulation qualified for one sequence of plasma exposure, plating chemistry, and dielectric cures can fail in another through delamination, excessive modulus, poor release, or contamination left after debonding.
Total-thickness variation adds another path from temporary processing to permanent yield. A small thickness change across the carrier stack can shift lithographic focus, alter RDL dimensions, change pillar or pad height, and leave the final bonding surface with a local offset. Microbumps can tolerate part of that offset through solder deformation, but the direct copper-dielectric interface has little capacity to accommodate it. The absence of compliance turns small thickness differences into incomplete bonds.
“With hybrid bonding, we’re talking about zero die-to-die distance, so everything there is rigid. The dielectric is rigid, the copper is rigid, the whole wafer is rigid,” said Derami. “If your thickness variation is a little bit higher than what this system can accommodate, you’re going to get non-bonding. You might get bonding at the center, non-bonding at the edge, and there’s nothing to accommodate for this. There’s no bump.”
Lower temperature, same electrical result
The thermal budget creates another boundary between a bond that can be formed and a product that can survive after forming it. The dielectric surfaces establish initial contact, but annealing strengthens the interface, allowing the recessed copper pads to expand and reconstruct into a continuous electrical path. Conventional conditions provide useful kinetics, but they can expose completed devices to temperatures and stresses that were not part of their original process qualification, a problem that grows more pronounced in heterogeneous stacks combining logic, memory, RF, sensors, and photonic devices.
“In order to strengthen this bonding at the interface, and in order to do what we call a copper reconstruction at the interface, we need to increase the temperature,” said CEA-Leti’s Najem. “Usually, the temperature that is applied is higher than 300 °C, so typically it’s 400 °C for one or two hours. The challenge is that this temperature is really high, and it might not be compatible with some applications, such as memory.”
Lower-temperature work is consequently aimed at achieving the same electrical and mechanical results using a different combination of surface activation, copper structure, time, and chemistry. CEA-Leti reported annealing a wafer-to-wafer test vehicle at 100 °C, followed by morphological and electrical characterization that showed low resistance and high electrical yield. That result establishes technical possibility under the reported test conditions, but production adoption will require reliability data, application-specific thermal cycling, and confirmation that the process remains stable across incoming variation and throughput conditions.
The right target is not the lowest temperature that produces one successful sample. Manufacturers need the lowest thermal budget that preserves bond strength, resistance, yield, and long-term reliability for the devices being integrated. That window may differ substantially by product and by workload, which makes a universal hybrid-bonding recipe less likely as the application space expands.
Look before you leap
None of these controls can guarantee that every interface will form correctly, but they can prevent obvious risks. Macro optical inspection can identify scratches, edge damage, large particles, coating anomalies, and spatial hot spots before more expensive metrology, probe, or bonding steps, while electrical test provides a second view of whether a visible anomaly is functionally meaningful.
“We could do it either pre- or post-probe. I always liked to do it post, because I got to see what the prober results were going to be,” said Errol Akomer, applications director at Microtronic. “Would it pass or fail based on electrical test versus what I’m seeing optically in line?”
Once that relationship is established, screening can move earlier in the flow, reducing unnecessary probe touchdowns and preventing suspect material from entering higher-value assembly steps. The objective is not for macro inspection to resolve the hybrid-bonding interface directly, but to reserve slower and more expensive analysis for defects that require it.
One process window, many companies
The final obstacle is organizational as much as technical because the relevant process window now crosses supplier boundaries. A materials company may know how a cleaning or temporary bonding formulation responds to temperature and chemistry, while the equipment company knows the force, timing, and local environment inside the tool. The fab or OSAT sees the incoming variation and final yield, but each participant may receive only a narrow specification from the one before it.
That model works when interfaces between process modules have generous margins. Fine-pitch hybrid bonding reduces those margins until information hidden inside one supplier’s qualification becomes necessary to understand another supplier’s result. Cleaning chemistry, equipment sequence, queue time, wafer shape, and pad design can no longer be optimized as separate commercial boxes. Faster iteration will require selective transparency across those boundaries.
“You have a chemistry person, an equipment person, and a fab person, and each hands the next a black box. The equipment guy asks the chemistry guy for a material, develops his process around what comes out, and tells the fab, ‘Here’s the solution from my black box,’” said Bhatt. “What we need is transparency between these boxes so we can iterate faster, because there’s not going to be one solution that fits all. Every process is going to require some customization.”
That transparency does not require companies to abandon their intellectual property. It requires enough shared characterization to determine how a material changes equipment behavior, how the equipment changes surface condition, and how those effects appear in electrical yield, while test and inspection data travel far enough upstream to identify the step that first moved.
The same fragmentation appears on the design side, where the rules governing pad layout, redundancy, and keep-out regions must reflect measured process distributions rather than ideal geometry.
“There has been effort to define ADKs [advanced packaging design kits], but those efforts have not yielded a universal definition so far,” said Amlendu Shekhar Choubey, senior director of product management at Synopsys. “There has to be a concerted effort to make sure that all these components which are coming into play have a shared design language. Ecosystem partners, EDA vendors, foundries, OSATs, and the lead customers need to play a role in that.”
Conclusion
Fine-pitch hybrid bonding can go to high volume, but the answer will not come from proving the bond mechanism one more time. Wafer-to-wafer production has already shown that carefully prepared surfaces can be joined at scale, a companion article shows how wafer-scale parallelism makes enormous interconnect populations possible. The harder work is preserving those conditions when the manufacturing flow begins selecting, thinning, transporting, cleaning, aligning, and bonding dies one at a time.
The next stage is making the manufacturing flow scale with the fabric it creates. Fine-pitch hybrid bonding will become broadly manufacturable where fabs, OSATs, equipment makers, materials suppliers, designers, and test engineers treat the bond as the final expression of one connected process rather than a discrete operation at the end of the line.
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