Memory Access In AI Systems


Memory access is a key consideration in AI system design. Ron Lowman, strategic marketing manager for IP at Synopsys, talks about how memory affects overall power consumption, why partitioning of on-chip and off-chip is so critical to performance and power, and how this changes from the cloud to the edge. » read more

Moving Data And Computing Closer Together


The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Making Sense Of PUFs


As security becomes a principal design consideration, physically unclonable functions (PUFs) are seeing renewed interest as new players emerge onto the market. PUFs can play a central role in hardware roots of trust (HRoTs), but the messaging in the market can make it confusing to understand the different types of PUF as well as their pros and cons. PUFs leverage some uncertain aspect of som... » read more

NVM Reliability Challenges And Tradeoffs


This second of two parts looks at different memories and possible solutions. Part one can be found here. While various NVM technologies, such as PCRAM, MRAM, ReRAM and NRAM share similar high-level traits, their physical renderings are quite different. That provides each with its own set of challenges and solutions. PCRAM has had a fraught history. Initially released by Samsung, Micron, a... » read more

Memory Issues For AI Edge Chips


Several companies are developing or ramping up AI chips for systems on the network edge, but vendors face a variety of challenges around process nodes and memory choices that can vary greatly from one application to the next. The network edge involves a class of products ranging from cars and drones to security cameras, smart speakers and even enterprise servers. All of these applications in... » read more

Scaling Up Compute-In-Memory Accelerators


Researchers are zeroing in on new architectures to boost performance by limiting the movement of data in a device, but this is proving to be much harder than it appears. The argument for memory-based computation is familiar by now. Many important computational workloads involve repetitive operations on large datasets. Moving data from memory to the processing unit and back — the so-called ... » read more

HBM Issues In AI Systems


All systems face limitations, and as one limitation is removed, another is revealed that had remained hidden. It is highly likely that this game of Whac-A-Mole will play out in AI systems that employ high-bandwidth memory (HBM). Most systems are limited by memory bandwidth. Compute systems in general have maintained an increase in memory interface performance that barely matches the gains in... » read more

An Increasingly Complicated Relationship With Memory


The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

Software In Inference Accelerators


Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Balancing Flexibility And Quality In SRAM Verification


Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

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