tag: SRAM

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference" was published by researchers at FZI Research Center for Information Technology and Karlsruhe Institute for Information Technology (KIT). Abstract: "Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural network... » read more

Comparative Analysis of CFET and NSFET Architectures (TU Munich, IIT)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET" was published by researchers at TU Munich and Indian Institute of Technology. Abstract "This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature ... » read more

The Competitive Advantage Of SRAM PUF Technology
By Vincent van der Leest - 09 Oct, 2025 - Comments: 1

By Vincent van der Leest and Geert-Jan Schrijen In the article from 2024, "SRAM PUF: The Secure Silicon Fingerprint", we explored the fundamentals of SRAM-based Physical Unclonable Functions (PUFs) and their role as a secure, cost-effective, and scalable solution for cryptographic (root) key generation and storage. SRAM PUF technology leverages the unique physical properties of silicon to c... » read more

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)
By Technical Paper Link - 06 Oct, 2025 - Comments: 0

A new technical paper titled "CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing" was published by researchers at University of California, Riverside. Abstract "Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software librari... » read more

Performance And Energy Characterization Of A Commercial Compute-in-SRAM Device (Cornell, USC, MIT, GSI)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device" was published by researchers at Cornell University, USC, MIT and GSI Technology Inc. Abstract "Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evalu... » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)
By Technical Paper Link - 05 Sep, 2025 - Comments: 0

A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

LtRAM And StRAM: Specialized Memory Architectures Leveraging Workload-Specific Access Characteristics (Stanford, Microsoft)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "Towards Memory Specialization: A Case for Long-Term and Short-Term RAM" was published by researchers at Stanford University and Microsoft, and an independent researcher. Abstract "Both SRAM and DRAM have stopped scaling: there is no technical roadmap to reduce their cost (per byte/GB). As a result, memory now dominates system cost. This paper argues for a parad... » read more

Noise Margin Enhancing ULVR SRAM Cell (Tokyo Institute of Technology)
By Technical Paper Link - 06 Aug, 2025 - Comments: 0

A new technical paper titled "A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity" was published by researchers at the Tokyo Institute of Technology. Excerpt "A new ultralow-voltage retention (ULVR) SRAM cell is proposed, which can highly enhance the noise margin (NM) for the ULVR mode at ultralow voltages (VUL). This 8T cell is configured with newtype Schmitt-trigger (ST) i... » read more

LLM Inference: Core Bottlenecks Imposed By Memory, Compute Capacity, Synchronization Overheads (NVIDIA)
By Technical Paper Link - 01 Aug, 2025 - Comments: 0

A new technical paper titled "Efficient LLM Inference: Bandwidth, Compute, Synchronization, and Capacity are all you need" was published by NVIDIA. Abstract "This paper presents a limit study of transformer-based large language model (LLM) inference, focusing on the fundamental performance bottlenecks imposed by memory bandwidth, memory capacity, and synchronization overhead in distributed ... » read more

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms" was published by Georgia Tech. Abstract "In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth... » read more

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