Chip Industry Week In Review


Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Chip Industry Technical Paper Roundup: June 8


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 🔗 imec, KU Leuven ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs 🔗 KAIST Thermal- and Aging-Aware Rowhamme... » read more

Accelerating Zero-Knowledge Proof Generation With Reconfigurable Hardware (KAIST)


Researchers from Korea Advanced Institute of Science and Technology (KAIST) have published “ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs”. Abstract “Zero-knowledge proofs (ZKP) allows a prover to convince a verifier of computational correctness without revealing private data, ensuring both privacy and verifiability. However, proof generation i... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Research Bits: May 11


Non-destructive terahertz inspection Researchers from Adelaide University, Virginia Diodes, the Hasso Plattner Institute, and the University of Potsdam used terahertz waves to observe electrical activity inside fully packaged semiconductor devices as they are operating. The technique relies on an ultra-sensitive detection system using a specialized homodyne quadrature receiver, which can pi... » read more

Chip Industry Technical Paper Roundup: May 5


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Direct... » read more

Chip Industry Week in Review


Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Energy-Efficient Liquid Cooling for Advanced Semiconductor Packaging (KAIST)


A new technical paper, "Highly energy-efficient manifold microchannel for cooling electronics with a coefficient of performance over 100,000," was published by researchers at KAIST. The study presents a CMOS-compatible manifold microchannel cooler that removes over 2,000 W/cm² using single-phase water at only 8 kPa pressure drop, achieving a record COP of 106,000—a significant improvement... » read more

Chip Industry Technical Paper Roundup: Apr. 21


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Neural Computers 🔗 Meta AI, KAUST Characterizing tip-sample interaction dynamics on EUV nanostructures using AFM with a high-aspect ratio tip 🔗 Purdue University, Intel, Bruker  Photonic chip packaging for extreme environments ὑ... » read more

SSD Emulator For Massively Parallel, GPU-Centric Storage (KAIST)


A new technical paper, "SwarmIO: Towards 100 Million IOPS SSD Emulation for Next-generation GPU-centric Storage Systems," was published by KAIST. Abstract "GPU-initiated I/O has emerged as a key mechanism for achieving high-throughput storage access by leveraging massive GPU thread-level parallelism, while recent industry trends point toward SSDs optimized for ultra-high random-read IOPS.... » read more

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