tag: Baya Systems

Wafer-Scale vs. Chiplets: The New War? Part 1
By Nandan Nayampally - 28 May, 2026 - Comments: 0

Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

Overcoming Bottlenecks In Data Movement
By Ed Sperling - 27 May, 2026 - Comments: 0

AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

From Standards To Systems: The Chiplet Era On Arm
By Nandan Nayampally - 30 Apr, 2026 - Comments: 0

For three decades, Arm didn’t just participate in industry transformation — it redefined it. From mobile to cloud to automotive, Arm’s architecture and the AMBA ecosystem have become the backbone of scalable compute. Now the industry faces its next structural shift: The era of monolithic SoCs is tapering and giving way to the era of chiplet systems. While complex SoCs are going to b... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets
By Liz Allan - 30 Apr, 2026 - Comments: 0

Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

AI Workloads Are Turning The Data Center Network Into A Combined Memory And Storage Fabric
By Saurabh Gayen - 26 Mar, 2026 - Comments: 0

Recent industry trends, including the release of NVIDIA’s Rubin platform (developer.nvidia.com), point to a growing consensus that AI inference is reshaping data center architecture in a fundamental way. As inference workloads become dominant, the data center network is no longer just a communication layer between servers. It is increasingly part of a distributed memory and storage hierarchy,... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Data Boom Puts Pressure On NoCs, Fabrics
By Liz Allan - 26 Mar, 2026 - Comments: 0

Key Takeaways: NoC challenges, such as wiring congestion, timing closure, and performance, must be considered in tandem with topology and placement. Topologies can be customized to meet an application’s specific data flow needs, with a system containing multiple topologies to suit different data or zones. What is challenging for one type of system, such as an SoC, switch, or AI chi... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

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