Beyond The RISC-V ISA


For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

DO-254 Solutions Blueprint


The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL simulator, synthesis, place & route and static timing analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including requirements management, traceability, tests management, de... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

What Makes A Good AI Accelerator


The rapid growth and dynamic nature of AI and machine learning algorithms is sparking a rush to develop accelerators that can be optimized for different types of data. Where one general-purpose processor was considered sufficient in the past, there are now dozens vying for a slice of the market. As with any optimized system, architecting an accelerator — which is now the main processing en... » read more

What Is SOTIF?


Arteris IP’s Kurt Shuler discusses new system-level best-practices approach to automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles. https://youtu.be/nC3TkF7c0Oo » read more

Solving Systemic Complexity


EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

The Week In Review: Design


M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

The Week In Review: Design


Tools & IP Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up. ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be adde... » read more

Preparing For Bigger Changes Ahead


The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

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