5G OTA Test Not Ready For Production


5G is poised to dominate the wireless world, but over-the-air (OTA) testing of 5G beamforming antennas is still not ready for volume production. Beamforming is a critical element in the millimeter wave version of 5G, because of the limitations of ultra-high-frequency signals. Unlike 4G and its predecessors, millimeter wave technology will not penetrate objects, so signals need to be directed... » read more

HW/SW Design At The Intelligent Edge


Adding intelligence to the edge is a lot more difficult than it might first appear, because it requires an understanding of what gets processed where based on assumptions about what the edge actually will look like over time. What exactly falls under the heading of Intelligent Edge varies from one person to the next, but all agree it goes well beyond yesterday’s simple sensor-based IoT dev... » read more

How Far Can AI Go?


AI is everywhere. There are AI/ML chips, and AI is being used to design and manufacture chips. On the AI/ML chip side, large systems companies and startups are striving for orders of magnitude improvements in performance. To achieve that, design teams are adding in everything from CPUs, GPUs, TPUs, DSPs, as well as small FPGAs and eFPGAs. They also are using small memories that can be read i... » read more

Auto Reliability At The System Level


Carmakers and chipmakers are approaching autonomous vehicle design from very different perspectives, and while they both talk about safety and reliability as the end goals, they have widely divergent ideas about how to get there. All of this is just beginning to come into focus as carmakers vie for leadership in the autonomous vehicle space, and much of it appears to hinge on the definition ... » read more

New Design Approaches At 7/5nm


The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Can AI, 5G Chips Be Verified?


AI and 5G bode well for the semiconductor industry. They will require many billions of new, semi-customized and highly complex chips from the edge all the way to the data center, and they will require massive amounts of engineering time and tooling. But these technologies also are raising lots of questions on the design and verification front about what else can be automated and how to do it. ... » read more

Beyond The RISC-V ISA


For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

DO-254 Solutions Blueprint


The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL simulator, synthesis, place & route and static timing analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including requirements management, traceability, tests management, de... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

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