tag: Vinci

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Foundation Model For Physics: The Next Layer Of Intelligence For Engineering
By John Bruggeman - 28 May, 2026 - Comments: 0

Over the past decade or so, foundation models have emerged as the dominant paradigm for interacting with language, images, and code. Large Language Models (LLMs) can generate text. Vision models can interpret images. Multimodal systems can connect the two seamlessly. But one domain has not yet seen the same foundation-model-level shift: validated, deterministic reasoning over the physical wo... » read more

Deterministic, Solver-Accurate Thermal and Warpage Analysis at Manufacturing Resolution for Advanced 2.5D HBM Packages
By Vinci - 27 May, 2026 - Comments: 0

Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging. Modern packages integrate high-power ASICs with multiple High Bandwidth Memory (HBM) stacks on a silicon interposer, creating tightly coupled thermal and mechanical interactions. Die-to-die thermal crosstalk elevates HBM junction temperatures, while coefficient of thermal e... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Using AI To Monitor Dashboards In Chips And Systems
By Ed Sperling - 06 May, 2026 - Comments: 0

Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

From Simulation Checkpoints To Continuous Physics
By Satish Radhakrishnan - 04 May, 2026 - Comments: 0

Semiconductor engineering teams have long relied on an iterative simulation workflow: define the scenario, prepare the model, run the analysis, review the results, adjust the design, and repeat until a decision can be made. That workflow remains essential. Simulation is still one of the primary ways teams evaluate physical behavior before hardware is built. But as chips, packages, and system... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Startup Funding: Q4 2025
By Jesse Allen - 19 Jan, 2026 - Comments: 0

The promise of AI dominated the last quarter of 2025. Investors were eager to claim stakes in both brand-new startups and more established companies developing AI-specific hardware, primarily for data centers, with over $1 billion alone flowing into the sector. The largest round of the quarter went to a new entrant aiming to fundamentally change how AI compute is performed, while two in-memory ... » read more

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