tag: Vinci

Observability Is A Missing Layer In AI-Era Chiplet Design
By Ann Mutschler - 01 Jul, 2026 - Comments: 0

Key Takeaways: In chiplet-based architectures, observability must be designed as a fabric-aligned, cross-die telemetry plane so architects can correlate traffic, latency, congestion, and fault behavior across package boundaries without losing system context. AI can extract value from high-volume silicon telemetry only when the architecture provides consistent instrumentation, near-senso... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Continuous Physics Reasoning:
Definition, Minimum Criteria, and the Role of Foundation Models for Physics
By Vinci - 24 Jun, 2026 - Comments: 0

Abstract Physical products are increasingly constrained by thermal, mechanical, electrical, and manufacturing realities, yet much of industry still relies on intermittent, expert-mediated physics evaluation. As systems become more complex and tightly coupled, this limits not only product development, but also manufacturing readiness, operational efficiency, and lifecycle performance. This p... » read more

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Foundation Model For Physics: The Next Layer Of Intelligence For Engineering
By John Bruggeman - 28 May, 2026 - Comments: 0

Over the past decade or so, foundation models have emerged as the dominant paradigm for interacting with language, images, and code. Large Language Models (LLMs) can generate text. Vision models can interpret images. Multimodal systems can connect the two seamlessly. But one domain has not yet seen the same foundation-model-level shift: validated, deterministic reasoning over the physical wo... » read more

Deterministic, Solver-Accurate Thermal and Warpage Analysis at Manufacturing Resolution for Advanced 2.5D HBM Packages
By Vinci - 27 May, 2026 - Comments: 0

Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging. Modern packages integrate high-power ASICs with multiple High Bandwidth Memory (HBM) stacks on a silicon interposer, creating tightly coupled thermal and mechanical interactions. Die-to-die thermal crosstalk elevates HBM junction temperatures, while coefficient of thermal e... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

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