More detailed roadmaps are needed to guide how the industry stacks, connects, powers, and cools tomorrow’s chips.
Heterogeneous integration requires comprehensive roadmaps to support collaboration across the design and manufacturing of the next generation of semiconductor products and the systems they support. A global team of researchers from a broad spectrum of industry, academia, and research institutes led by Intel has published a perspective in the March 2026 issue of Nature Reviews Electrical Engineering1, positioning that heterogeneous integration — an architecture, design, and advanced packaging approach that combines separately manufactured chips and components into a single system — is now essential to sustaining progress in AI, smartphones, and next-generation wireless communications. While HI capabilities have advanced rapidly since 2010, the authors propose that existing industry roadmaps have not evolved at the same pace, creating research and coordination gaps that could hinder the future electronics ecosystem. These risks in roadmap clarity could slow technology readiness, misalign research investments, and limit supply chain preparedness.
The core challenges in AI progress are scale and hardware energy efficiency. AI computing demands are now doubling every three months, driven by the constant shuttling of data between processors and memory. Even when memory is placed close to a chip, moving information back and forth consumes enormous energy. Until this bottleneck is addressed, faster AI hardware will continue to come at a steep environmental and economic cost.
The team draws on examples including AI accelerators, 5G/6G infrastructure, autonomous systems, and aerospace and harsh environments to illustrate where heterogeneous integration is already enabling progress — and where further advances are required. To sustain this momentum, the authors call for a new generation of technology roadmaps with clear, measurable targets for the building blocks that underpin future electronic systems.
The collaboration behind the paper — spanning companies including Intel, ASE, Texas Instruments, 3MTS, and Boeing, in addition to research institutions including Lawrence Berkeley National Laboratory and National Laboratory of the Rockies, as well as academic institutions including University of Toronto, Binghamton University, Penn State University, Arizona State University, University of Illinois Urbana-Champaign, Purdue University, and UCLA — reflects the cross-sector engagement the authors argue is essential to guide the industry.
Heterogeneous integration offers a powerful solution to the scaling and energy challenges facing AI systems. Instead of integrating all functions on a single monolithic die, HI assembles processors, memory, power delivery, communications, and photonic components into a tightly coupled package.
Vertical integration, one of the most impactful versions of this approach, involves stacking chips connected through dense, fine-pitch interconnects — dramatically shortening data-movement distances, and reducing both latency and energy consumption. High-bandwidth memory (HBM) already exploits this approach by stacking multiple memory dies in a single package. Extending such close coupling between logic and memory is a key pathway to higher performance, more energy efficient AI hardware.
Realizing the full potential of heterogeneous integration will require coordinated advances across interconnects, power delivery, and thermal management — areas where the team identifies gaps in current technology roadmaps.
Hybrid bonding is already enabling major gains in chip-to-chip interconnect density, bandwidth, and energy efficiency, but it also introduces new reliability challenges at bonding interfaces — pointing out the need for further research and refined design methodologies. In parallel, power delivery has become a limiting factor as AI workloads scale, motivating the integration of efficient voltage regulation within the package using technologies such as gallium nitride. These pressures are compounded by thermal constraints as vertical integration intensifies, and transistor counts approach the trillion-device range. This drives further interest in advanced cooling approaches, including liquid cooling embedded within chip stacks, and reinforces the need to co-design power, performance, and thermal management as a unified system. Increased integration along with reduced feature sizes due to increased interconnect densities require more focus on ensuring reliability of complex heterogeneous structures. This includes a focus on modeling the thermo-mechanical states of the packages, anticipating potential failure modes, and developing manufacturable solutions.
Improved industry roadmaps matter because heterogeneous integration is as much a coordination challenge as a technical one, spanning system architects, designers, manufacturers, materials suppliers, and integrators across the global electronics ecosystem. Although the IEEE Heterogeneous Integration Roadmap2 provides a valuable overview of the HI landscape, the authors bring attention to limitations in two key respects: it lacks quantified, time-bound projections for critical technology attributes, and it does not consistently articulate the strategic research challenges required to achieve long-term system goals.
To address these gaps, the authors propose more ambitious, rolling 20-year roadmaps that provide device‑ and application-level projections, and incorporate digital twins to model performance and reliability prior to fabrication. In addition, roadmaps should explicitly link system needs to improvements in materials, processes, and design tools.
Heterogeneous integration marks a shift from building bigger chips to building smarter systems. This shift is especially urgent for AI, where moving data rather than performing calculations now dominates energy use. HI also plays a critical role in advancing 5G/6G as millimeter wave radios drive extreme integration density, and in aerospace systems, where commercial packaging approaches must be qualified for harsh environments and long operational lifetimes.
Looking further ahead, the integration of photonics promises to lift longstanding bandwidth and energy constraints, potentially redefining how data centers and advanced computing platforms are built. Achieving these advances will require roadmaps that look decades ahead and coordinate innovation across materials, design, manufacturing, and reliability.
Co-authors include William Chen, ASE (US) Inc.; Patrick Thompson, Texas Instruments; Wilmer Bottoms, Third Millennium Test Solutions (3MTS); Amr S. Helmy, University of Toronto; Benson Chan, Binghamton University; Madhavan Swaminathan, Penn State University; John Shalf, Lawrence Berkeley National Laboratory; Christopher Bailey, Arizona State University; Jose Schutt-Aine, University of Illinois Urbana-Champaign; Ganesh Subbarayan, Purdue University; Timothy Lee, Boeing; Subramanian S. Iyer, University of California at Los Angeles; Sreekant Narumanchi, National Laboratory of the Rockies; and Rajiv Mongia, Intel.
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