Chip Industry Week In Review


Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Chip Industry Technical Paper Roundup: Mar. 24


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations NL2GDS: LLM-aided interface for Open Source Chip Design 🔗 University of Bristol, Rutherford Appleton Laboratory An Integrated Failure and Threat Mode and Effect Analysis (FTMEA) Framework with Quantified Cross-Domain Correlation Factors for Automot... » read more

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)


A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Chip Industry Technical Paper Roundup: Sept 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=469 /] Find more semiconductor research papers here. » read more

Electrochemical Absorption of Hydrogen in Structured Palladium Thin-Film Electrodes (Univ. of Bristol)


A new technical paper titled "Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices " was published by researchers at the University of Bristol. Abstract "Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between th... » read more

Chip Industry Technical Paper Roundup: July 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=456 /] Find more semiconductor research papers here.   » read more

Volatile And Non-Volatile NEM Switches Fabricated In A CMOS-Compatible SOI Foundry Platform (KTH, U. of Bristol, EPFL, Imec)


A new technical paper titled "Volatile and non-volatile nano-electromechanical switches fabricated in a CMOS-compatible silicon-on-insulator foundry process" was published by researchers at KTH Royal Institute of Technology, University of Bristol, EPFL, imec, and Ghent University. Abstract "Nanoelectromechanical (NEM) switches have the advantages of zero leakage current, abrupt switching ch... » read more

Research Bits: June 17


Superlattice castellated FETs Researchers from the University of Bristol and Northrop Grumman Mission Systems discovered a latch-effect in gallium nitride (GaN) that could lead to improved radio frequency device performance, crucial for enabling 6G devices. “We have piloted a device technology, working with collaborators, called superlattice castellated field effect transistors (SLCFETs),... » read more

Chip Industry Week in Review


To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

Chip Industry Technical Paper Roundup: Apr. 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=416 /] Find more semiconductor research papers here. » read more

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