Chip Industry Technical Paper Roundup: July 22

Thermal issues related to hybrid bonding of 3D-stacked HBM; GAA metrology; data center architecture for LLMs; CPU fuzzers; planarization for layouts in advanced nodes; rowhammer attacks on GPUs; photonic SRAM for fast IMC; colloidal coordination nanosheets; physics-based ASICs; NEM switches in a SOI foundry process.

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New technical papers recently added to Semiconductor Engineering’s library:

Name of Paper Research Organizations
Thermal Issues Related to Hybrid Bonding of 3D-Stacked HBM: A Comprehensive Review Chungbuk National University
3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography Cornell University, ASM and TSMC
Scaling Intelligence: Designing Data Centers for Next-Gen Language Models Intel Corporation and Georgia Tech
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection ETH Zurich
Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes Fraunhofer IPMS
GPUHammer: Rowhammer Attacks on GPU Memories are Practical University of Toronto
X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing University of Wisconsin–Madison and USC
Rationally Engineered Heterometallic Metalladithiolene Coordination Nanosheets with Defined Atomic Arrangements Tokyo University of Science
Solving the compute crisis with physics-based ASICs Normal Computing Corporation, ARIA, UCSB et al.
Volatile and non-volatile nano-electromechanical switches fabricated in a CMOS-compatible silicon-on-insulator foundry process KTH Royal Institute of Technology, University of Bristol, EPFL, imec, and Ghent University

Find more semiconductor research papers here.

 



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