Natural-language chip design; automotive semiconductor risk assessment; wafer-on-wafer hybrid bonding; rad-hard NAND; neuromorphic computing; monolithic 3D DRAM; ECC-aware chiplet interconnects; AI system validation with digital twins.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| NL2GDS: LLM-aided interface for Open Source Chip Design 🔗 |
University of Bristol, Rutherford Appleton Laboratory |
| An Integrated Failure and Threat Mode and Effect Analysis (FTMEA) Framework with Quantified Cross-Domain Correlation Factors for Automotive Semiconductors 🔗 |
Robert Bosch |
| Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding 🔗 |
ETH Zurich |
| Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack 🔗 |
Georgia Tech |
| Protonic nickelate device networks for spatiotemporal neuromorphic computing 🔗 |
UCSD, Rutgers University |
| System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures 🔗 |
Georgia Tech |
| Link Quality Aware Pathfinding for Chiplet Interconnects 🔗 |
UCLA |
| Towards Structured Training and Validation of AI-based Systems with Digital Twin Scenarios 🔗 |
RWTH Aachen University, RIF e.V. |
Find more semiconductor research papers here.
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