Chip Industry’s Technical Paper Roundup: Apr. 10

TPU v4-three major features; survey on ML in HW security; simulation environment with customized RISC-V instructions for LIM architectures; RF energy harvesting and wireless power transfer technologies; two-dimensional ferroelectricity in a single-element; heterogeneous RISC-V compute cluster for extreme-edge on-chip DNN Inference and training.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings Google
A Survey on Machine Learning in Hardware Security TU Delft
Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente
RF Energy Harvesting and Wireless Power Transfer for Energy Autonomous Wireless Devices and RFID LTCI, Télécom Paris, Institut Polytechnique de Paris, Universidade de Aveiro, The Hague, McGill University, University of Bordeaux, Polytechnique Montreal, and others
Two-dimensional ferroelectricity in a single-element bismuth monolayer National University of Singapore, Zhejiang University, Tianjin University, and University of Chinese Academy of Sciences
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training University of Bologna and ETH Zurich

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