Flash Getting Stacked High-Bandwidth Version


Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

AFMTJ Model For In-Memory Computing (University of Arizona)


University of Arizona researchers published "Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study." Abstract "Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulation framework integrating multi-sublattice Landau-Lifshitz-Gilb... » read more

Comprehensive System-Level Performance Model For p-SRAM-Based IMC (USC, UW-Madison)


Researchers at USC and University of Wisconsin-Madison published "System-Level Performance Modeling of Photonic In-Memory Computing." Abstract "Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level performa... » read more

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)


A new technical titled "Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications" was published by researchers at Seoul National University. Abstract "This work presents, for the first time, an investigation of the impact of random phase distribution on ferroelectric (FE) tunnel field-effect transist... » read more

Verification and Reliability Methods For RRAM-Based Computing-in-Memory (Univ. of Bremen et al)


A new technical paper titled "Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory" was published by researchers at University of Bremen, DFKI GmbH, University of Florida and TU Munich. Abstract "Computing-in-memory (CIM) has gained immense traction owing to the benefits it provides in power, performance, and area. CIM can be don... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)


A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)


A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)


A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)


A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

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