Chip Industry’s Technical Paper Roundup: June 13

Quantum algorithm co-design activities; data processing of FPGAs; modeling nanosheet GAAFETs;  extreme fast charging of Li-ion batteries; 3D IC routing; solid-state batteries; area-efficient PIM architecture; power hardware-in-the-loop.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Data Processing with FPGAs on Modern Architectures ETH Zürich
NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance Politecnico di Torino
Extreme fast charging of commercial Li-ion batteries via combined thermal switching and self-heating Approaches Lawrence Berkeley National Laboratory, University of California, Berkeley, and Hong Kong University of Science and Technology

On Legalization of Die Bonding Bumps and Pads for 3D ICs Georgia Institute of Technology, NVIDIA Corporation, and University of Bremen

Tailoring of the Anti-Perovskite Solid Electrolytes at the Grain-Scale Oak Ridge National Laboratory

Simulating Noisy Quantum Circuits for Cryptographic Algorithms Virginia Tech
FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications Rochester Institute of Technology and George Mason University

Multi-rate Discrete Domain Modeling of Power Hardware-in-the-Loop Setups Karlsruhe Institute of Technology

Further Reading
Technical Paper Home

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