Chip Industry Technical Paper Roundup: Mar. 9


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption 🔗 Boston University, Northeastern University, KAIST, University of Murcia Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler ... » read more

Extending Formal Verification to Sequential Circuits (U. of Bremen)


Researchers from University of Bremen have released “Linear Formal Verification of Sequential Circuits using Weighted-AIGs”. Abstract "Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verifica... » read more

LLM- Based Techniques To Support Behavior-Driven Development For HW Design (U. of Bremen, DFKI)


A new technical paper titled "LLM-based Behaviour Driven Development for Hardware Design" was published by researchers at University of Bremen/DFKI. Abstract "Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineerin... » read more

Chip Industry Technical Paper Roundup: Dec. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=499 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review.   » read more

Verification and Reliability Methods For RRAM-Based Computing-in-Memory (Univ. of Bremen et al)


A new technical paper titled "Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory" was published by researchers at University of Bremen, DFKI GmbH, University of Florida and TU Munich. Abstract "Computing-in-memory (CIM) has gained immense traction owing to the benefits it provides in power, performance, and area. CIM can be don... » read more

Technical Paper Roundup: November 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=167 /] More Reading Technical Paper Library home » read more

A HIL Methodology For The SoC Development Flow


A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

Chip Industry’s Technical Paper Roundup: June 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=109 /] Further Reading Technical Paper Home » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact


A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

Week In Review: Design, Low Power


Cadence rolled out a slew of new products at this week’s CDNLive Silicon Valley, including: A new generative AI-powered tool for analog, mixed-signal, RF and photonics design; An extended collaboration with TSMC and Microsoft to advance giga-scale physical verification system in the cloud; A multi-year partnership with the San Francisco 49ers football organization, focused on sust... » read more

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