Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase


A new technical paper “Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans – A RISC-V Case Study” was published by researchers at University of Bremen, DFKI GmbH, and the German Aerospace Center.

“With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT devices. Besides, the insertion of a Hardware Trojan (HT) into a chip after the in-house mask design is outsourced to a chip manufacturer abroad for fabrication is a significant source of concern. Though abundant HT detection methods have been investigated based on side-channel analysis, physical measurements, and functional testing to overcome this problem, there exists stealthy HTs that can hide from detection. This is due to the small overhead of such HTs compared to the whole circuit.

In this work, we propose several novel HTs that can be placed into a RISC-V core’s post-layout in an untrusted manufacturing environment. Next, we propose a non-invasive analytical method based on contactless optical probing to detect any stealthy HTs. Finally, we propose an open-source library of HTs that can be used to be placed into a processor unit in the post-layout phase. All the designs in this work are done using a commercial 28nm technology.”

Find the technical paper here. Published January 2023.

Sajjad Parvin, Mehran Goli, Frank Sill Torres, and Rolf Drechsler.
2023. Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware
Trojans – a RISC-V Case Study. In 28th Asia and South Pacific Design Automation Conference (ASPDAC ’23), January 16–19, 2023, Tokyo, Japan. ACM, New
York, NY, USA, 7 pages. https://doi.org/10.1145/3566097.3567919

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