Chip Industry’s Technical Paper Roundup: Feb. 14

Connecting quantum chips; HW trojans post-layout design RISC-V; thermal contact resistance; ferroelectric 5nm; emulating racetrack memories on FPGA; SAT-based attacks; RISC-V virtualization; improving ML model’s reliability; substrate routing for wire-bonding FBGA package design; stress Issue of vertical connections in 3D integration for HBM applications.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
A high-fidelity quantum matter-link between ion-trap microchip modules University of Sussex, Universal Quantum Ltd, University College London and University of Bristol
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans – A RISC-V Case Study University of Bremen, DFKI GmbH, and the German Aerospace Center
Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers UT Arlington
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration Universidade do Minho (Portugal), University of Bologna, and ETH Zurich
Thickness scaling down to 5 nm of ferroelectric ScAlN on CMOS compatible molybdenum grown by molecular beam epitaxy University of Michigan, with DARPA funding
Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications National Yang Ming Chiao Tung University
“ERMES: Efficient Racetrack Memory Emulation System based on FPGA University of Calabria and TU Dresden
ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design National Taiwan University of Science and Technology
Post-hoc Uncertainty Learning using a Dirichlet Meta-Model MIT, University of Florida, and MIT-IBM Watson AI Lab (IBM Research)
RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks University of Southern California

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