Chip Industry Technical Paper Roundup: July 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=426 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow


As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)


A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Chip Industry Technical Paper Roundup: June 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=436 /] Find more semiconductor research papers here. » read more

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)


A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

A Survey Of Digital Twins and Other Prototyping Technologies for Vehicles


A new technical paper titled "Digital Twin Technologies for Vehicular Prototyping: A Survey" was published by researchers at Central Michigan University and University of Florida. Abstract "Digital Twin (DT) technology is widely regarded as one of the most promising tools for industry development, demonstrating substantial application across numerous cyber-physical systems. Gradually, this ... » read more

Chip Industry Technical Paper Roundup: Apr. 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=421 /] Find more semiconductor research papers here. » read more

Chip Industry Week In Review


Don't have time to read this? Check out Semiconductor Engineering's Inside Chips podcast.  The U.S. Department of Commerce is investigating TSMC for potential export control violations involving Huawei chips, reports Reuters. The probe follows TechInsights' teardown of a Huawei AI accelerator chip last year. The foundry, meanwhile, maintains it has not shipped any chips to Huawei since 2020... » read more

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