Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Tools Needed To Track, Catalog Hardware Vulnerabilities


Monitoring for cyberattacks is a key component of hardware-based security, but what happens afterward is equally important. Logging and cataloging identified hardware vulnerabilities to ensure they are not repeated is essential for security. In fact, thousands of weak points have been identified as part of the chip design process, and even posted publicly online. Nevertheless, many companies... » read more

Chip Industry Technical Paper Roundup: Nov. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=386 /] » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)


A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)


A technical paper titled "A Survey on SoC Security Verification Methods at the Pre-silicon Stage" was recently published by researchers at University of Florida. Abstract "This paper presents a survey of the state-of-the-art pre-silicon security verification techniques for System-on-Chip (SoC) designs, focusing on ensuring that designs, implemented in hardware description languages (HDLs) a... » read more

Chip Industry Technical Paper Roundup: Oct. 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=371 /]   More Reading Chip Industry Week In Review AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more. Technical Paper Library home » read more

Chip Industry Week In Review


Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

Physics-Based Efficient Device Model for Fe-TFTs (Univ. of Florida)


A new technical paper titled "An efficient device model for ferroelectric thin-film transistors" was published by researchers at University of Florida. Abstract "Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectivel... » read more

Securing Advanced Packaging Supply Chain With Inherent HW Identifiers Using Imaging Techniques


A new technical paper titled "Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging" was published by researchers at University of Florida and University of Cincinnati. "This work visits the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches, and proposes the notion of inherent... » read more

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