Hardware Virtualization Support in the RISC-V CVA6 Core


A new technical paper titled “CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration” was written by researchers at Universidade do Minho (Portugal), University of Bologna, and ETH Zurich.

Abstract Excerpt: “In this article, we describe our work on hardware virtualization support in the RISC-V CVA6 core. Our contribution is multifold and encompasses architecture, microarchitecture, and design space exploration. In particular, we highlight the design of a set of microarchitectural enhancements (i.e., G-Stage Translation Lookaside Buffer (GTLB), L2 TLB) to alleviate the virtualization performance overhead. We also perform a design space exploration (DSE) and accompanying post-layout simulations (based on 22nm FDX technology) to assess performance, power and area (PPA). Further, we map design variants on an FPGA platform (Genesys 2) to assess the functional performance-area trade-off.”

Find the technical paper here (preprint). February 2023.

Sá, Bruno, et al. “CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.” arXiv preprint arXiv:2302.02969 (2023).

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