Chip Industry’s Technical Paper Roundup: June 13

New technical papers recently added to Semiconductor Engineering’s library: [table id=109 /] Further Reading Technical Paper Home » read more

Multi-Rate Discrete-Time Modeling Approach Of A Power Hardware-in-the-Loop Setup (Karlsruhe Institute of Technology)

A technical paper titled “Multi-rate Discrete Domain Modeling of Power Hardware-in-the-Loop Setups” was published by researchers at the Institute for Technical Physics, Karlsruhe Institute of Technology, Karlsruhe, Germany. Abstract: "Power Hardware-in-the-Loop (PHIL) facilitates the testing of novel power engineering solutions in the lab, allowing a flexible testing environment while kee... » read more

Split Additive Manufacturing for Printed Neuromorphic Circuits (Karlsruhe Institute of Technology)

A new technical paper titled "Split Additive Manufacturing for Printed Neuromorphic Circuits" was published by researchers at Karlsruher Institut für Technologie (KIT). Abstract: "Printed and flexible electronics promises smart devices for application domains, such as smart fast moving consumer goods and medical wearables, which are generally untouchable by conventional rigid silicon tech... » read more

Managing EDA’s Rapid Growth Expectations

The EDA industry has been doing very well recently, but how long this run will continue is a matter of debate. EDA is an industry ripe for disruption due to rapid changes in chip architectures, end markets, and a long list of new technologies. In addition, recent geopolitical tensions are bringing a lot more attention to this small sector upon which the whole semiconductor industry rests. De... » read more

Bridging IC Design, Manufacturing, And In-Field Reliability

Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management and how that can potentially glue together design, manufacturing, and devices in the field, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer sci... » read more

Week In Review: Design, Low Power

Intellectual Property Flex Logix inked an agreement with the Air Force Research Laboratory, Sensors Directorate (AFRL/RY) covering any Flex Logix IP technology for use in all US Government-funded programs for research and prototyping purposes with no license fees. “Our first license with AFRL for EFLX eFPGA in GlobalFoundries 12nm process was highly successful, with more than a half dozen pr... » read more

Manufacturing Bits: Dec. 21

Tiny electronic fountain pens Karlsruhe Institute of Technology (KIT) and Taiyuan University of Technology have developed what resembles a tiny electronic fountain pen, a technology that can pattern and deposit small structures on surfaces. The system from KIT and Taiyuan University is actually a high-precision tabletop microplotter, which is used to print or deposit materials for printed e... » read more

Can Coherent Optics Reduce Data-Center Power?

As optical bandwidth requirements increase, system designers are turning to “coherent” modulation schemes that can place more data on the same laser light, and lower power over long connections. A newer question is whether those savings could be achieved for short connections within data centers, as well. “Coherent is the direction everything's moving, because for a given system and... » read more

New Memories Add New Faults

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM

Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chi... » read more

← Older posts