Chip Industry Week In Review


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Framework For Early Anomaly Detection In AMS Components Of Automotive SoCs


A technical paper titled “Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning” was published by researchers at University of Texas at Dallas, Intel Corporation, NXP Semiconductors, and Texas Instruments. Abstract: "Given the widespread use of safety-critical applications in the automotive field, it is crucial to ensure the Functional Safety (FuSa) ... » read more

Technical Paper Roundup: November 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=167 /] More Reading Technical Paper Library home » read more

Hybrid Photoresist Capable Of High-Resolution, Positive-Tone EUVL Patterning


A technical paper titled “Vapor-Phase Infiltrated Organic–Inorganic Positive-Tone Hybrid Photoresist for Extreme UV Lithography” was published by researchers at Stony Brook University, Brookhaven National Laboratory, and University of Texas at Dallas. Abstract: "Continuing extreme downscaling of semiconductor devices, essential for high performance and energy efficiency of future microe... » read more

Research Bits: November 14


Solid-state thermal transistor for heat management Researchers from University of California Los Angeles created a stable and fully solid-state thermal transistor that uses an electric field to control a semiconductor device’s heat movement. It is compatible with integrated circuits in semiconductor manufacturing processes. The team’s design incorporates the field effect on charge dynamics... » read more

Chip Industry’s Technical Paper Roundup: October 24


New technical papers added to Semiconductor Engineering’s library this week. [table id=157 /] More Reading Technical Paper Library home » read more

GNN-Based Pre-Silicon Power Side-Channel Analysis Framework At RTL Level


A technical paper titled “SCAR: Power Side-Channel Analysis at RTL-Level” was published by researchers at University of Texas at Dallas, Technology Innovation Institute and University of Illinois Chicago. Abstract: "Power side-channel attacks exploit the dynamic power consumption of cryptographic operations to leak sensitive information of encryption hardware. Therefore, it is necessary t... » read more

Chip Industry’s Technical Paper Roundup: May 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=103 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Research Bits: March 6


2D TMDs on silicon Engineers at MIT, University of Texas at Dallas, Institute for Basic Science, Sungkyunkwan University, Washington University in St. Louis, University of California at Riverside, ISAC Research, and Yonsei University found a way to grow 2D materials on industry-standard silicon wafers while preserving their crystalline form. Using a new “nonepitaxial, single-crystalline g... » read more

Technical Paper Round-Up: June 8


  New technical papers added to Semiconductor Engineering’s library this week. [table id=32 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

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