SLAC energy estimates across computing; LLM performance on AI accelerators; LLMs for HW test; power side channel analysis; vertical power delivery; CNNs on embedded automotive systems; in memory computing; multi-bit CAM designs using FeFETs.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining | SLAC National Laboratory and Stanford University |
| A Comprehensive Performance Study of Large Language Models on Novel AI Accelerators | Argonne National Laboratory, State University of New York, and University of Illinois |
| LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation | University of Cambridge, lowRISC, and Imperial College London |
| SCAR: Power Side-Channel Analysis at RTL-Level | University of Texas at Dallas, Technology Innovation Institute and University of Illinois Chicago |
| Vertical Power Delivery for Emerging Packaging and Integration Platforms – Power Conversion and Distribution | University of Illinois Chicago |
| Performance/power assessment of CNN packages on embedded automotive platforms | University of Modena and Reggio Emilia |
| First demonstration of in-memory computing crossbar using multi-level Cell FeFET | Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich |
| SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search | Zhejiang University, China, Georgia Institute of Technology, University of California Irvine, Rochester Institute of Technology, University of Notre Dame, and Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province |
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