Chip Industry Week In Review

Samsung’s next-gen process, memory and assembly roadmap; 3D metrology In 3D chips/packages; Russian IC sanctions; domain-specific AI chips; CHIPS Act funding; Black Semi’s +$200M windfall; HW security failures.


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company also said it would introduce 3D integration combined with 2.5D vertical integration, offering up to 21 times more bandwidth with speeds of up to 70.5 TB/second.

In conjunction with the event, EDA companies announced certifications and IP availability for Samsung Foundry processes:

  • Alphawave Semi expanded its range of IP available on Samsung Foundry, bringing IP for PCIe 7.0, 112G and 224G Ethernet, and the latest UCIe die-to-die interconnect standard to Samsung’s SF5, SF4, and SF2 processes.
  • Cadence‘s digital and analog tools have been optimized for Samsung Foundry’s SF2 and the complete backside implementation flow has been certified for the SF2 node, while its 3D-IC technology has been enabled for all of Samsung Foundry’s multi-die integration offerings.
  • Siemens and Samsung Foundry announced updated process design kits (PDKs) and evaluated Siemens’ High Density Advanced Packaging (HDAP) flow for the foundry’s multi-die-integration packaging process. Various Siemens tools were certified for Samsung’s advanced process nodes.
  • Synopsys’ AI-driven digital design and analog design flows were certified for Samsung Foundry’s SF2 process with multiple test chip tapeouts. The Samsung SF2 process was optimized using Synopsys’ design technology co-optimization (DTCO) solution, which will also be used for the SF1.4 process.

The U.S. State Department announced more than 300 new sanctions against Russia and other organizations, businesses, and financial entities that help support Russia’s unprovoked war in Ukraine. The sweeping new sanctions affect multiple companies, including Hong Kong-based Superchip and Kvantek, which export ICs and other microelectronic devices to Russia.

RocketLab was awarded $28.9 million by the U.S. Commerce Department under the CHIPS Act, aiming to expand production of compound semiconductors for spacecraft and satellites by 50% in the next three years.

Flow Computing emerged from stealth with €4 million (~$4.3M) in pre-seed funding and what it calls a Parallel Processing Unit, which it claims can be integrated on-die to drastically increase CPU performance by addressing latency, synchronization, and virtual level parallelism.

Black Semiconductor received €254.4 million (~$273.9 M) in its Series A and from Europe’s IPCEI ME/CT program to build its pilot line in Aachen, Germany, for mass production in 2031. The startup developed a co-integrated optics system based on graphene as a translator to convert electronic signals into optical signals and vice versa.

Quick links to more news:

Market Reports
Product News
Events and Further Reading


Three chip manufacturers in Oregon will receive $36.2 million in funding from the state’s CHIPS Act. Siltronic was awarded $2.2 million to modernize its Portland facility, Analog Devices received $12 million to expand its Beaverton facility, and Lam Research will get $22 million for a new research and development lab at its Tualatin campus.

Toshiba plans to invest about $636 million to expand its semiconductor operations over the next three years, reports Mainichi Japan.

MKS Instruments announced plans to build a “super factory” in Malaysia, with groundbreaking expected to begin next year.

South Korean AI chip startups Rebellions and Sapeon announced plans to merge, according to SK Telecom, Sapeon’s parent company. Both currently are focused on developing NPUs for data center inferencing. The two also received significant investments: Rebellions, backed by telecom KT Corp., raised a $124 million Series B round in January, while Sapeon has received over $100 million from SK Group companies and outside investors. The deal is expected to be completed by the end of the year.

Siltronic opened its second 300mm wafer fab in Singapore at JTC’s Tampines Wafer Fab Park. The $2 billion fab is not expected to reach full production capacity for several years.

France-based Kalray and Israeli startup Pliops intend to merge, focusing on improved data acceleration SoCs for AI and storage. Kalray will hold majority control over the merged entity.

Mining firm Rare Earths Norway claims to have discovered Europe’s largest rare earths deposit.

The European Commission announced provisional tariffs on Chinese EVs, subject to an investigation. BYD: 17.4%; Geely: 20%; SAIC: 38.1%; and 21% for other BEV producers in China, which cooperate in the investigation but have not been sampled.


Semiconductor Engineering published its Low Power-High Performance newsletter this week, featuring:

And its Test, Measurement & Analytics newsletter featured reports on:

Plus, more reporting this week:


Researchers at ETH Zurich showed the RISC-V ecosystem also is impacted by Rowhammer. The work will be presented at DRAMSec 2024  in late June.

University of Massachusetts and Worcester Polytechnic Institute researchers evaluated probing attacks against chiplets.

Todd Austin, professor of CSC at University of Michigan, added a seventh video to his recent hardware security collection, focusing on 14 new hardware security attacks in the last several years, including Spectre-based attacks, novel side channel attacks, and memory isolation failures. Find his full playlist here. 

Temperature has become an object of fascination to security researchers due to the vagaries of how the physical properties of heat affect performance.  Here’s how heat can be used to crash a system or device entirely or pose a threat, via temperature-based side channel attacks.

The National Institute of Standards and Technology (NIST) is seeking public comment on its report, Hardware Security Failure Scenarios: Potential Weaknesses in Hardware Design, through July 31, 2024. The authors leveraged existing work to provide a catalog of 98 security failure scenarios, each with a statement on how hardware can be exploited, where it can occur, and what kind of damage is possible.

The University of Cincinnati published a student’s PhD dissertation: “Efficient Techniques for Logic Locking.”

The Common Weakness Enumeration (CWE) asked for feedback on its changes to the presentation of CWE entries on the CWE website, and announced an Artificial Intelligence Working Group (AI WG) is accepting new members.

The EU Agency for Cybersecurity (ENISA) is now authorized as a CVE numbering authority and can also publish vulnerabilities. Also, the EU Council published a summary of its cybersecurity policies.

The Cybersecurity and Infrastructure Security Agency (CISA) issued a number of alerts/advisories.

Markets and Money

Revenues decreased 4.3% quarter-over-quarter for the top 10 global foundries in Q1 2024, according to TrendForce. The reduction is primarily attributed to seasonal order reductions for consumer electronics and economic headwinds for automotive and industrial market.

DRAM revenues increased 5.1% in Q1 2024, reaching $18.35 billion, while shipments experienced an expected seasonal decline in shipments compared to the previous quarter, reports TrendForce. DRAM prices are expected to increase by an additional 13% to 18% in Q2 2024.

The penetration rate of AI notebooks is predicted to soar from 1% in 2024 to 20% in 2025, reports TrendForce. The annual shipment of AI NBs is expected to reach 173.45 million units in 2024 at a year over year growth rate of 3.6%.

In smartphone markets news from Counterpoint, Colombia’s Q1 2024 shipments grew 27% YoY, Germany’s Q1 2024 shipments grew 13% YoY, driven by Samsung. And realme is the most popular brand in the 16 to 25 age group in India.

Product News

Synopsys unveiled a complete PCIe 7.0 IP solution, consisting of controller, IDE security module, PHY, and verification IP that enables up to 512 GB/s data transfers for compute-intensive AI workloads.

Rambus introduced its PCIe 7.0 IP portfolio, which includes controller, retimer, and multi-port switch, along with an in-IP debug/logic analyzer to support first-silicon bring-up.

Alphawave Semi taped out an off-the-shelf multi-protocol I/O connectivity chiplet on TSMC’s 7nm process that supports Ethernet, PCIe, CXL and UCIe and delivers a total bandwidth of up to 1.6 Tbps.

Flex Logix announced its eXpreso eFPGA compiler achieved 98.6% LUT packing density and is now shipping to alpha customers for evaluation with production slated for later 2024.

Infineon had several announcements this past week:

  • Power System Reliability Modeling to reduce data center power shortages and blackouts. An algorithm runs on a digital power controller, integrating software and hardware and acting as a bridge between component and system reliability;
  • An expanded portfolio of next-gen OptiMOS 7 MOSFETs for automotive applications, available in 40 V,  80 V, and 100 V, and optimized for all standard and future automotive 48 V applications;
  • It will provide customers with detailed product carbon footprint data, starting now with about half its portfolio.
  • A 600 V CoolMOS S7TA Superjunction MOSFET for automotive power management applications, featuring an integrated temperature sensor that improves the accuracy of junction temperature sensing, well suited for solid-state relay (SSR) applications.

Esperanto Technologies selected Arteris’ CSRCompiler SoC integration automation software to develop its next generation of energy-efficient RISC-V SoCs for AI inference and HPC workloads in data center and enterprise-edge applications.

Keysight Technologies and SmartViser teamed up to provide a solution to evaluate the battery consumption performance of smartphones and tablets to meet the European Union’s Energy Efficiency Index (EEI) energy labeling mandate.


Siemens and KU Leuven partnered to support educational activities for digital twins and to research digital twins for smart and sustainable products.

Fig. 1: Siemens and KU Leuven digital twin technology. Source: Siemens

imec reported on a memory effect in ovonic threshold switching (OTS) devices that paves the way to a new compute express link (CXL) memory.

MIT researchers:

  • Demonstrated a chip-based 3D printer, an optical device that could enable rapid prototyping on the go.
  • Developed a computer vision method for characterizing a material’s electronic properties up to 85 times faster than existing technology.
  • MIT and MIT-IBM Watson AI Lab researchers used LLMs to help robots navigate.
  • MIT-CSAIL researchers created an algorithm that discovers language by watching videos.

Oak Ridge National Laboratory (ORNL) researchers used AI for autonomous discovery and optimization of materials.

Fig. 2: In this artist’s conception of the process, an automated deposition system places a new material onto a base material. Credit: Chris Rouleau/ORNL, U.S. Dept. of Energy

A new imager chip that can “see” through walls or inside packages was announced by researchers at the University of Texas at Dallas and Seoul National University. The imager emits electromagnetic signals in the 300-GHz frequency band between microwave and infrared. The chip could be used in mobile devices, which must be held within an inch of the object to be scanned to produce an image.


Keysight Technologies and Japan’s National Institute of Advanced Industrial Science and Technology (AIST) will collaborate on quantum technology research and industrialization, focusing on quantum control technologies, low-temperature electronics device technology, and modeling and simulation, as well as standardization efforts.

Diraq says it achieved a control accuracy of 99.9% for a qubit manufactured by imec using industry-standard CMOS materials on a 300mm silicon wafer. Diraq is also teaming with GlobalFoundries to create a chip that monolithically integrates silicon qubit devices with standard transistors.

Researchers at Leibniz Supercomputing Centre, TU Munich, and IQM Quantum Computers published “Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center.

Researchers from TU Delft and TNO’s QuTech found a route to scalable Majorana qubits by creating devices that exploit the combined material properties of superconductors and semiconductors, to help solve quantum computing challenges.

Events and Further Reading

Find upcoming chip industry events here, including:

Event Date Location
Standards for Chiplet Design with 3DIC Packaging (Part 1) Jun 14 Online
2024 IEEE Symposium on VLSI Technology & Circuits Jun 16 – 20 Honolulu
AI Hardware and Edge AI Summit: Europe Jun 18 – 19 London, UK
SNUG Taiwan Jun 19 Zhubei City, Taiwan
Standards for Chiplet Design with 3DIC Packaging (Part 2) Jun 21 Online
DAC 2024 Jun 23 – 27 San Francisco
RISC-V Summit Europe 2024 Jun 24 – 28 Munich
Leti Innovation Days 2024 Jun 25 – 27 Grenoble, France
ISCA 2024 Jun 29 – Jul 3 Buenos Aires, Argentina
SEMICON West Jul 9 – 11 San Francisco
Find All Upcoming Events Here

Upcoming webinars are here.

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