Research Bits: June 8


Multi-tasking transistor Researchers at Pohang University of Science & Technology (POSTECH) developed a zinc oxide (ZnO) and tellurium (Te) heterojunction transistor technology that exhibits negative differential transconductance (NDT), where current decreases over a certain voltage range. By precisely controlling overlap length between the two materials, the team realized double negati... » read more

Chip Industry Technical Paper Roundup: Dec. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=499 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review.   » read more

Heat Dissipation in Solid-State Nanopore (Univ. of Osaka et al)


A new technical paper titled "Gate-Tunable Ionothermoelectric Cooling in a Solid-State Nanopore" was published by researchers at the University of Osaka, the University of Tokyo, National Institute of Advanced Industrial Science and Technology et al. The paper states: "Efficient heat dissipation at the nanoscale remains a major challenge for high-performance microelectronics. Here, we dem... » read more

Research Bits: Dec. 2


Ionothermoelectric cooling Researchers from the University of Osaka, University of Tokyo, and Japan's National Institute of Advanced Industrial Science and Technology proposed an ionothermoelectric cooling strategy for chips that enhances cooling by driving the flow of ions through nanoscale channels. “We fabricated a nanosized pore in a semiconductor membrane and surrounded the nanopore ... » read more

Chip Industry Week in Review


The U.S. government announced new import tariff actions and deals this week, including: The EU: 15% tariff on most goods including semiconductors. According to the EU's president, the action excludes semiconductor equipment. Copper: 50% tariff on all imports of semi-finished copper products and intensive copper derivative products, effective Aug. 1, but raw input material is excluded. ... » read more

Chip Industry Week In Review


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Chip Industry Week In Review


Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

Chip Industry Technical Paper Roundup: April 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=214 /] Find last week’s technical paper additions here. » read more

Hybrid All-Optical Switching Devices Combining Silicon Nanocavities And 2D Semiconductor Material


A new technical paper titled "Hybrid silicon all-optical switching devices integrated with two-dimensional material" was published by researchers at RIKEN, National Institute of Advanced Industrial Science and Technology (AIST), and Keio University. Abstract "We propose and demonstrate hybrid all-optical switching devices that combine silicon nanocavities and two-dimensional semiconduct... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

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