RISC-V virtualization; hexagonal boron nitride for enhanced graphene device array; human–machine collaboration for improving process development; NIST HW-based confidential computing; ferroelectric HEMT; SpGEMM with RISC-V vector instructions; wafer defects; reducing contact resistance on 2D transistors; approximate accelerators in FPGA-based systems.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| CVA6 RISC-V Virtualization : Architecture, Microarchitecture, and Design Space Exploration | Universidade do Minho, University of Bologna, and ETH Zurich |
| Optimization of SpGEMM with Risc-V vector instructions | Barcelona Supercomputing Center |
| WS2 Transistors with Sulfur Atoms Being Replaced at the Interface: First-Principles Quantum-Transport Study | National Yang Ming Chiao Tung University |
| Fully epitaxial, monolithic ScAlN/AlGaN/GaN ferroelectric HEMT | University of Michigan |
| SEMI-PointRend: Improved Semiconductor Wafer Defect Classification and Segmentation as Rendering | imec, University of Ulsan, and KU Leuven |
| autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems | TU Wien, Brno University of Technology, and NYUAD |
| Hardware Enabled Security: Hardware-Based Confidential Computing | NIST |
| Human–machine collaboration for improving semiconductor process development | Lam Research |
| Large-area synthesis and transfer of multilayer hexagonal boron nitride for enhanced graphene device arrays | Kyushu University, National Institute of Advanced Industrial Science and Technology (AIST), and Osaka University |
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