Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

New Approach to Encoding Optical Weights for In-Memory Photonic Computing Using Magneto-Optic Memory Cells


A new technical paper titled "Integrated non-reciprocal magneto-optics with ultra-high endurance for photonic in-memory computing" was published by researchers at UC Santa Barbara, University of Cagliari, University of Pittsburgh, AIST and Tokyo Institute of Technology. Abstract "Processing information in the optical domain promises advantages in both speed and energy efficiency over existi... » read more

Chip Industry Technical Paper Roundup: April 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=214 /] Find last week’s technical paper additions here. » read more

Week In Review: Design, Low Power


Arm is helping to address the ongoing talent shortage through its newly announced Semiconductor Education Alliance, with a long list of partners, including Arduino, Cadence, Cornell University, Semiconductor Research Corp., STMicroelectronics,Synopsys, Taiwan Semiconductor Research Institute, the All-India Council for Technical Education, and the University of Southampton. The Alliance... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Large Area Synthesis of 2D Material Hexagonal Boron Nitride, Improving Device Characteristics of Graphene


A new technical paper titled "Large-area synthesis and transfer of multilayer hexagonal boron nitride for enhanced graphene device arrays" was published by researchers at Kyushu University, National Institute of Advanced Industrial Science and Technology (AIST), and Osaka University. Abstract "Multilayer hexagonal boron nitride (hBN) can be used to preserve the intrinsic physical properti... » read more

Chip Industry’s Technical Paper Roundup: Feb. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=82 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology


A new technical paper titled "Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique" by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). "We have developed a technique for measuring the sidewall of the resist pattern using atomic for... » read more

Chip Industry’s Technical Paper Roundup: Jan. 31


New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration


A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

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