Chip Industry’s Technical Paper Roundup: Jan. 31

Spectre attack via cache on RISC-V; wafer-level transfer of graphene; silent data corruptions; multi-core accelerators; autonomous driving E/E architectures; failure tolerant training w/persistent memory disaggregation over CXL; 3 terminal magnetic thermal transistor.


New technical papers added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
A three-terminal magnetic thermal transistor Rice University
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment University of Electro-Communication, Academy of Cryptography Techniques, TRASIO, and AIST
Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements Infineon Technologies AG, RWTH Aachen University, Protemics, and Advantest.
Mitigating silent data corruptions in HPC applications across multiple program inputs University of Iowa, Baidu Security, and Argonne National Lab
Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks KU Leuven and TU Munich
Multi-objective optimization for safety-related available E/E architectures scoping highly automated driving vehicles Robert Bosch GmBbH and University of Luxembourg
Failure Tolerant Training with Persistent Memory Disaggregation over CXL KAIST and Panmnesia

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