Automated Security Assertion Generation Using LLMs (U. of Florida)


A new technical paper, "Assertain: Automated Security Assertion Generation Using Large Language Models," was published by University of Florida. Abstract "The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property verification. This paper presents Assertain, an automated ... » read more

Chip Industry Week in Review


The U.S. is considering annual approvals for Samsung and SK hynix to export chipmaking tools and materials to their factories in China, replacing perpetual waivers granted under the validated end user system, reports Bloomberg. The proposal, presented by the U.S. Commerce Department to South Korean officials, would require the companies to reapply each year for specific quantities of restricted... » read more

Chip Industry Technical Paper Roundup: Sept 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=469 /] Find more semiconductor research papers here. » read more

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)


A new technical paper titled "2025 Most Important Hardware Weaknesses" was published by researchers at Hardware CWE Special Interest Group. Excerpt "The Most Important Hardware Weaknesses (MIHW) empowers organizations with the knowledge to proactively strengthen hardware security and reduce risks at the source. The 2025 CWE MIHW represents a refreshed and enhanced effort to identify and edu... » read more

Chip Industry Week In Review


The EU’s tariffs on semiconductors will not exceed 15%, according to Trump’s latest trade deal. In addition, the EU committed to purchasing at least $40 billion worth of U.S. AI chips as well as other investments. [FAQ is here.] Lifelines for Intel: Intel inked a deal to sell the U.S. government a 10% non-voting equity stake in its business, worth $8.9 billion. The stake will be fun... » read more

Metrics And Methodology for Hardware Security Constructs (NIST)


A new technical paper titled "Metrics and Methodology for Hardware Security Constructs" was published by NIST. Abstract "Although hardware is commonly believed to be security-resilient, it is often susceptible to vulnerabilities arising from design and implementation flaws. These flaws have the potential to jeopardize not only the hardware's security, but also its operations and critical us... » read more

Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Chip Industry Week In Review


SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Chip Industry Week In Review


Concerns mount on the use of American-manufactured semiconductors in Russian weapons, with Analog Devices, AMD, Intel and TI set to testify next week before the U.S. Senate Permanent Subcommittee on Investigations. Also, U.S. and other government agencies issued a joint advisory and more details about ongoing Russian military cyberattacks, espionage, and sabotage. The U.S. Commerce Departmen... » read more

Chip Industry Week In Review


Three Fraunhofer Institutes (IIS/EAS, IZM, and ENAS) launched the Chiplet Center of Excellence, a research initiative to support the commercial introduction of chiplet technology. The center initially will focus on automotive electronics, developing workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The UCIe Consortium published the Un... » read more

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