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Design Challenges Increasing For Mixed-Die Packages

The good and bad of assembling dies from different foundries.

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The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore’s Law, making heterogeneous combinations of die easier, cheaper, and more predictable.

There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to the broadest selection of available IP, along with the ability to have the best IP available for a particular application, developed using the optimal process technology, and at the right price point. It also makes it possible to leverage OSATs for assembly and test, rather than relying solely on foundries, opening the door to a wide choice of suppliers and different packaging options.

There are other less obvious impacts from this multi-die or multi-chiplet design approach, as well. For one thing, it likely will increase competition between foundries, which could lead to lower-cost chipsets, according to John Ferguson, DRC product management director at Siemens EDA.

In addition, it allows governments and companies in highly competitive markets to utilize multiple foundries, both offshore and domestic. Whether that improves or decreases security may depend on the sources of various components, but it does ensure that no foundry has full access to the final design and all its IP.

“The HBMs may be coming from Samsung, and then you’re designing your processor, which is going to be a bigger challenge for the foundries,” said John Park, product management group director in the Custom IC & PCB Group at Cadence. “Does Samsung share a full wafer-level design with TSMC? The OSATs have been doing this forever. OSATs have integrated multiple dies from multiple different vendors for a long, long time because they weren’t seen as a foundry competitor. That may start to change, because now all the OSATs are offering their flavors of all these. It has the potential to become a huge ecosystem thing.”

That would have a big impact on relationships across the supply chain. “Who’s going to share their wafer with whom? You have to show the entire wafer, because whoever is going to build the interposers, they do the assembly,” Park said. “For instance, an OSAT would get a wafer, and they would bump it and dice it. The same sort of thing applies here. Now we start getting into the weeds of chip-first versus chip-last, or whether to mount the interposer to the package. The most reliable approach is to build the interposer independently, mount it to the BGA first, and then attach the die to it. The foundries now all have very, very tight relationships with the OSATs because they’ve got the ecosystem, and because at the end of the day, everything sits on a package. You can do all the advanced integration you want, but it’s useless until it gets put in a package and on a PCB.”

Fig. 1: Next-gen packaging/design impact. Source: Cadence

Fig. 1: Next-gen packaging/design impact. Source: Cadence

This also fundamentally alters the equation for derivative chips. Mixing die in interposer designs also enables reuse of previously designed chips for aggregation into multiple design assemblies, said Kevin Rinebold, advanced IC packaging technology specialist at Siemens EDA.

As a result, the focus now shifts to the best way to create a system and to optimize it for performance, power, and cost. But it also raises questions that design teams need to address, according to Kenneth Larsen, product marketing director at Synopsys. Among them:

  • How are designs disaggregated to make use of different technology nodes?
  • How are different kinds of technologies mixed?
  • How are tens or hundreds of chiplets handled?
  • How are designs scaled to potentially billions of connections between the die?
  • How are the HBMs and HBIs connected?
  • How are signals routed to ensure the integrity of those signals?
  • How are ECOs done, and if there is a change impacting the PCB, how is that handled?
  • How is analysis performed?

“All of this is connected together,” Larsen said. “There are microbumps, TSVs, microTSVs, and there are interfaces such as HBM and HBI. There are interconnections between die that have to be taken care of, as well.”

Alongside the benefits are a number of other aspects to keep in mind. “With a single supplier, if something goes wrong, you have a single point to work with to trace the root cause,” said Siemens EDA’s Ferguson. “With disaggregation, you either have to do it yourself, or you have to wade through information and finger-pointing across the ecosystem. It can also lead to more overhead for assemblers, such as supply chain and assembly rules that require common and/or compatible assembly rules.”

In addition, there is likely to be a significant reshuffling of responsibilities throughout the supply chain. “For the longest time, we’ve had a silicon team and a package team,” said Larsen. “It’s two different organizations that work together. But when you’re getting into these systems where there’s so much integration going on, the number of touchpoints between the teams goes up dramatically. The organization model is probably one of the things that will change over the coming years. I don’t know if it will become one team that’s responsible for the performance of the solution, one team that’s building this kind of system, or if it will continue to be two separate teams. By having all this silicon and technologies, and optimizing that together, I suspect it will become an IC challenge more than an integration challenge. Folks have to work closely together, that’s for sure.”

Responsibility and liability are major issues in the chiplet space. “From a business point of view, how do you handle the ownership of the different aspects of the design?” asked Manuel Mota, senior product marketing manager at Synopsys. “It’s an area that is evolving a lot, and is definitely something that needs to be addressed for the chiplet and multi-die market to make sense.”

In fact, the non-technical business issues may be more significant than the technology itself. To a large extent, many of the technology issues already have been solved. Intel, AMD, and Marvell all have successfully deployed chiplet strategies. But commercial, off-the-shelf chiplets are more difficult, in part because of the need for better characterization for off-the-shelf integration, and in part because there are differing opinions about how the pieces should go together and who’s responsible for different elements in those designs.

“In today’s organization model, there are systems designers, SoC front-end designers, SoC place-and-route engineers, power-thermal-noise engineers, the sign-off team, DFT, packaging, PCB teams, and all of those have to come together,” said Larsen. “There’s never been a place where you can see the entire system as one. Many folks have been using PowerPoint and Excel to sketch and then create their own flows to put things together. Maybe it works for now, but that’s going to break. It’s just too expensive, not only in building the flows, but also human involvement in the process. You cannot use your star engineers to maintain the flow. They need to be designing the next generations of chips.”

Having a common way of communicating between different groups and different teams that are building these big SoCs is critical. “This concerns the industry as a whole,” said Mota. “If you’re building this multi-die SoC from a 3D-IC in a single company, then it’s ultimately an internal flow that you need to define. But if you’re purchasing some of these die from other companies, or from foundries on a different process, etc., whatever you’re receiving needs to be integrated into this design flow. You need to come with a consistent set of collateral that enables you to insert it in a consistent design flow when you do your full validation, and this is something that still needs to evolve.”

The big challenge on the technology front is how to integrate all of these various chiplets using one or more standardized interconnect schemes.

“Interoperability in PHYs for die-to-die interfaces between different vendors chips/chiplets would be required, as well as much more complicated overall package assembly test due to interoperability between different DFT tools used for the different chips/chiplets,” said Anthony Mastroianni, advanced IC packaging solutions architect at Siemens EDA.

This includes the proper collateral, as well. But there has been progress over the past half-decade in developing data structures that work across different technologies from different foundries.

“Typically, IC tools work on a single die, single tech file, single rule,” Larsen noted. “We saw a need for expanding this data framework in order to mix and match technologies — for example, if you’re using 3nm from your favorite foundry and interposer technology from another company. Let’s say you end up with two dies on an interposer, in three different technologies. How do you bring that in and view it as one?”

Some of the collateral for each die/dielet/tile/chiplet can be brought in as a tech file. But there’s a place in which these two different things come together, and they have to hang together. For the space that’s not formulated in the technology files, how do you integrate with another vendor?

“We have worked with some of the foundries and some of the integration houses to figure out a way to exchange information between die,” Larsen said. “This is not IP protocols. It’s really, ‘You send your design to your OSAT. What kind of manufacturing requirements do you have when you do assembly? What kind of design rules should you check upfront when you go into this path or that path? How many of whatever that goes into the system do you need so you can manufacture and achieve high reliability and yield?’ There are new things being cooked up in the industry to support the concepts around how close can two die be put together with your foundry or your OSAT.”

Fig. 2: Example of multi-die system. Source: Synopsys

Fig. 2: Example of multi-die system. Source: Synopsys

The high cost of interposers
One of the limiters on some advanced packaging has been the cost of the interposer. “If you’re designing something super high volume, you need the form factor and you need the performance that you’re getting, so you’ll spend that extra money,” said Park. “However, more people are going to go to organic thin film where there is no TSV. It’s a board-like process, and not as fine a pitch as a silicon interposer. Silicon interposer is 1µm line, and the space is smaller. The thing to be wary of with interposers is there are lots of different types.”

Up until about 2010, packaging was largely an effort to shrink or encapsulate a PCB. “The tools, and various laminate styles or other sorts of substrates were PCB-like,” he said. “Then in 2011, with the introduction of Xilinx’s interposer, that changed the world. We are getting more IC requirements, which is interesting. There have always been requirements and technologies coming from the PCB side, but now with the foundries getting into this business, more input and methodologies and technologies are required from the chip domain. Designing a digital chip versus designing a multi-chip module, system, and package is night and day. The tools we use for one don’t work for the other.”

That said, more innovation is needed on the tool front to bring these worlds together, and to overcome the incredibly high price of design.

Questions across the ecosystem
With a shifting tool and manufacturing ecosystem, will ripples be felt widespread? Is it possible that the OSATs will take on more of the pie? Or will foundries continue to add new services on the packaging and assembly side? If Intel is any bellwether for the industry, other semiconductor companies may retool and move back to an IDM model.

“While Intel can do all things with its own fabs, including packaging, it’s not likely others will follow in the short term,” Park said. “Instead, the foundries have created friendly partnerships with OSATs. They realize that they need each other to get the design done. In the past when the foundries first got in the business, it looked like they were set on wiping out the OSATs, but they have since created partnerships. The number one and number two foundries now show partnerships with all of the various OSATs during presentations at technology conferences. Certainly, there are one-offs, like Intel, where it’s a one-stop shop. But this is the chiplet problem. We have these chiplets, and no one wants to share those either. If you’re an AMD or an Intel, you build your chiplet and you use it for your die-to-die packages that you’re putting together, but it’s unlikely that they would share that chiplet with the public. That’s the chiplet ecosystem hurdle. It probably will be 2025 before we have that figured out so I can go to a catalog and order off-the-shelf chiplets, add my special sauce, and then build it. That was the vision of DARPA’s CHIPS. We’re still working on it.”



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