New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology

How a real chip-last process flow with a chip-to-wafer (C2W) bonding technology can address the RDL-base Interposer PoP challenge.


Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced interconnection technology called a redistribution layer (RDL).

However, a PoP-type RDL-base platform requires dual-side RDLs on both top and bottom sides to stack another package on top. In a monolithic process flow, that means the second RDL only can be fabricated after finishing all the first RDL and the assembly processes such as flip-chip bonding, molding, and grinding. Therefore, this process flow is not quite as advantageous as a non-PoP type platform because chips can be lost during the second RDL process.

In this paper, to address this RDL-base Interposer PoP challenge, a real chip-last process flow with a chip-to-wafer (C2W) bonding technology is introduced. And the results are presented of building and testing an RDL-base wafer-level Interposer PoP with a size of 12.5 x 12.5 mm2 and thickness of 0.357 mm including solder ball. The bottom side has a 3-layer RDL structure and the top RDL for the package stacking has a 1-layer structure. These RDLs are implemented with copper (Cu) lines with 5 μm/10 μm of line & space (L/S) and copper (Cu) cored solder balls (CCSBs) are used as the vertical interconnect components. The silicon die and CCSBs’ joint quality is confirmed by reliability testing. The test vehicle package passed all the reliability tests of moisture resistance test (MRT) L3, Temperature Cycle, Condition B (TCB) 1,000 cycles, and high temperature storage (HTS) 1,000 hrs.

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