What’s So Different About Interposer Signal Integrity?

Dealing with unexpected challenges in advanced packaging.


By Kelly Damalou and Pete Gasperini
To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an impressive evolution over the last several decades. Their development encourages technological advancement in applications like high-performance computing, Artificial Intelligence (AI) processors, and Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips.

Stacked 3D-IC arrangements and side-by-side 2.5D-IC layout help designers surpass the limitations of Moore’s Law by making it feasible to achieve performance gains at the individual chip (or chiplet) level. Significant performance and cost gains can be  made with heterogeneous integration (HI) by using the most appropriate process technology for each chiplet in a 2.5D or 3D-IC assembly. While the benefits of HI are well understood, the laws of physics can still introduce novel challenges that can put the overall system performance at risk.

An important new feature of multi-die 2.5D-IC assemblies is the interposer, which carries the signal and power interconnect between chiplets. Interposers are most typically implemented as a large silicon chip with interconnect feature sizes based on mature process nodes like 65nm. High-speed digital busses transfer information between chiplets including high-performance graphics accelerators, network controllers, IO blocks, ML, SoCs, and high-speed memories. HI implies the addition of analog signals to custom chiplets like wireless communication and sensors. The benefits of 2.5D-IC comes with tradeoffs, including the need to confront new and exacerbated physics effects that monolithic chip designers typically don’t need to worry about. One of the most critical of these new concerns is high-accuracy signal integrity sign-off for interconnect on silicon interposers.

Understanding Signal Integrity (SI) on 2.5D Interposers
Signal Integrity is not a new problem. It is a standard part of analyzing any chip or printed circuit board (PCB). So, what makes SI for interposers different? The answer is an unprecedented combination of silicon density and speed at scales approaching those of PCBs. Traditional PCB tools don’t have the capacity to analyze interposers with many thousands or even millions of connections, while traditional IC tools for SI do not take into account the novel physical effects of large-scale structures like through-silicon vias (TSVs) or running high-speed signals over multiple centimeters – several orders of magnitude longer than on-chip interconnect.

Fig.1: Ansys RedHawk-SC Electrothermal analysis of the power distribution network (PDN) for a pair of chips on an interposer.

This combination has dramatically increased the number of multiphysics effects that need to be considered simultaneously for 2.5D and 3D-IC architectures, including ringing, crosstalk, ground bounce, signal distortion, signal loss, and power supply noise. The novelty of the technical challenge is reflected in the development of new communication protocols, like UCIe, specifically for interposers

Power Noise as a Source of Signal Noise
High-speed interfaces that operate at very high data rates, like Ethernet 112G/224G and PCIe‑6, are sensitive to power noise on the silicon power delivery network (PDN). Switching activity in nearby components can create a strong burst of current on the PDN that can cause dynamic voltage-drop (DVD)  and ringing. Parasitic capacitance and inductance in the power grid, together with decoupling capacitors, cause PDNs to behave as complicated RLC networks. Strong ringing on the PDN  will carry over to noise on signals driven through the silicon interposer. This can degrade system performance (timing error) or cause a functional failure. SI problems are often tightly connected to power integrity problems.  (Fig. 2).

Fig. 2: Switching activity can propagate a transient response on the PDN.

A particular category of power noise-induced SI is clock jitter. This affects the critical clock signals that are distributed to all components in order to keep them synchronized and operating in step with each other. A clock is supposed to toggle at a fixed frequency, but local dynamic voltage drop on the power supply can slightly delay or speed up the propagation of the clock signal. The result is a clock that ‘jitters’ and individual clock ticks randomly arrive a bit too early or a bit too late.

This means that high-frequency power delivery noise must be carefully analyzed so “noisy” digital blocks don’t cause spikes in the power distribution network and contribute to crosstalk in neighboring high-speed channels. Overall, power noise is problematic for sensitive analog functions and for high-speed and low-threshold/low-power CMOS devices.

Electromagnetic Coupling and Interference (EMC/EMI)
Interconnect running across an interposer between chiplets is high-speed, very close together, and very long by IC standards. This means designers – even digital designers – need to account for electromagnetic (EM) coupling between wires, the PDN, and chiplets. They must expect noise and parasitic effects to impact sensitive signals. Signal integrity signoff with electromagnetic accuracy is critical for achieving performance targets for the latest high-speed communication protocols like 3rd generation high bandwidth memory (HBM3). Electromagnetic analysis tools cannot extract a model for the entire 2.5D assembly in full detail. Selected sensitive signals should be co-extracted with the power distribution network and the resulting EM-coupled RLCk parasitic model can be merged with the RC parasitics. Maintaining and analyzing signal integrity under these conditions is a more nuanced pursuit because of the dense routing and high data rates that translate to high-frequency content.

Time Domain Circuit Simulation
Beyond the immediate challenge of delivering an accurate electromagnetic model for such a complex scenario, traditional signal integrity solutions aren’t equipped to deliver models that can be consumed by SPICE-level circuit simulators. High-speed applications inherently require time-domain analysis but circuit simulators have trouble converging time-domain simulations with traditional S-parameter models. As the number of ports in the S-parameter model increases, the circuit simulator faces even more difficulty converging on a solution. Leveraging an alternate format, like Rational Function Models (RFM), delivers the same level of accuracy with better efficiency for time-domain simulations or models with many ports.

Hierarchical Modeling of SI
However it is calculated, the complete SI picture of a 2.5D multi-chip design is too big for effective system-level analysis. System-level scale is best achieved through hierarchical modeling and reduced order models (ROMs) that capture the SI behavior at an appropriate level of detail for full system analysis with significantly smaller and faster models.

Organizational Challenges of Interposer Multiphysics
While companies may have all the requisite expertise in-house for 2.5D-IC design, it will nevertheless impose changes on traditional team dynamics. Today, top-level signal integrity analysis is often assigned to package or board-level design engineers who have experience with EM but limited experience with the silicon technologies and chip-level timing extraction methodologies used for silicon interposers. While the reverse is true for chip designers. Different groups have traditionally collaborated only late in the development cycle. Success in HI will require a closer realignment of distributed pockets of expertise into a single design team.

Ansys Multiphysics Platform for Interposer SI
As more and more electronics companies move into multi-die design, there’s a growing need for a multiphysics workflow that can provide insight into a wider variety of physics and their interactions throughout the design cycle—from individual chiplets to interposers and the complete system.

Ansys RedHawk-SC Electrothermal offers a comprehensive platform that leverages Ansys’ unparalleled range of physics engines (electrical, thermal, electromagnetic, mechanical, optical, and more) and deep silicon expertise to addresses the multiphysics challenges associated with 2.5D/3D-IC analysis. RedHawk-SC Electrothermal supports power integrity, signal, integrity, thermal integrity, and mechanical integrity analysis in a unified environment that seamlessly interfaces with all leading custom IC design platforms. Its SI power-noise analysis is based on industry-leading RedHawk-SC signoff technology, and the underlying SeaScape cloud-optimized big-data platform gives it the capacity for full-chip PDN analysis.

RedHawk-SC Electrothermal is capable of full system-level SI analysis thanks to its comprehensive Ansys Chip Signal Model (CSM) reduced order model that includes JEDEC-compatible timing, power noise, jitter, and slew modeling. CSM is used in the early prototyping stage to include system modeling of on-die chip signals as well as board-level PCB signals. The CSM reduced order model is generated for 2.5D/3D-IC silicon interposers with RedHawk-SC Electrothermal’s user-friendly interposer wizard that captures frequency-dependent electrical characteristics and considers power/ground effects on SI. CSM is ideal for optimizing IO/decap placement with a fast what-if analysis capability.

Ansys RaptorX is foundry-certified for on-chip electromagnetic modeling and is integrated into RedHawk-SC Electrothermal’s 3D-IC multiphysics analysis workflow to address signal integrity concerns in high-speed applications with electromagnetic accuracy.

Fig.3: A high-speed bus on a silicon interposer selected for fully coupled electromagnetic modeling with Ansys RaptorX.

With its unrivalled capacity and speed, RaptorX enables IC design engineers and signal integrity experts to accurately model the impact of electromagnetic coupling effects between selected structures throughout the complete design cycle—even for the most complex architectures like silicon interposers. It is able to read encrypted foundry technology files and uses an intuitive graphical user interface (GUI) that automates the setup of electromagnetic simulations in the context of IC design workflows. This allows designers to kick-start extractions in a matter of minutes.

RaptorX captures unintended crosstalk between more than 100 signals and the power distribution network with modest compute requirements that delivers good scalability on multiple CPUs and multiple machines.  It extracts an accurate model for electrical, magnetic, and substrate coupling for designs with many hundreds of ports in S-parameters format, which is well-suited for frequency-domain simulations, and in Rational Function Model (RFM) format, which is more efficient for time-domain simulations. RaptorX’s electromagnetic solver has been certified by TSMC and Samsung for 2.5D- and 3D-IC architectures, making it a trusted partner for the entire IC and silicon interposer design cycle.

In summary, 2.5D/3D-IC and interposers offer great potential but also pose some significant analysis and design challenges. Register now for the upcoming technical webinar Comprehensive Multiphysics Analysis Platform for 3D-IC Interposers to learn more about Ansys’ integrated multiphysics solution for power integrity, signal integrity, and thermal integrity of silicon interposers.

Pete Gasperini is a product marketing manager in the Electronics Business Unit at Ansys.

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