Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance

Using virtual fabrication to study profile variation in a 5nm finFET device.


Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (shallow trench isolation) profile on device performance in a 5 nm FinFET vehicle, and demonstrate how SEMulator3D virtual fabrication can help address profile variation issues[1].

In our study, an SRAM111 architecture was selected as the test structure. Using a combination of fin height and pattern dependence variation in a virtual split experiment, we analyzed the effect of STI footing/trenching, fin height imbalance and fin height profiles using SEMulator3D (see figure 1) [2].

Fig. 1: Final STI recess profile.

To evaluate the impact of the STI recess profile on device performance, an NMOS structure was cropped out of the SRAM and used in electrical performance modeling. During STI recess, different STI recess profile geometries were generated for testing. Figure 2 reveals the off-state leakage status across a selected drain voltage sweep range for different geometries. Larger footings and lower fin heights exhibited much higher off-state leakage and slightly lower on-current. These problems were not as large during changes in fin height imbalance. From the leakage curve, it is obvious that higher leakage is caused by increased DIBL (drain-induced barrier lowering) effects seen with lower fin heights and larger footings. The leakage current distribution was also visualized across cross-section profiles using SEMulator3D (see figure 3). The main contributing factor to leakage current appeared to be source drain punch through at the fin bottom.

Fig. 2: Drain leakage with drain voltage sweep.

Fig. 3: Leakage current distribution from different directions.

Based upon these results, we can see that both STI footing issues and imbalanced fin heights can lead to diminished gate control at the fin bottom, similar to the issues seen at a lower fin height. To overcome this problem, an optimal trenching STI profile can be designed which can both boost on-current conditions and lower off-leakage current.

These results demonstrate that rigorous STI profile control may be required to meet performance specifications in an advanced FinFET process setting.

Download the full whitepaper “Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance” to learn more.


  1. https://www.coventor.com/products/semulator3d
  2. Fried D et al, SISPAD 2014 Sep 9 (pp. 209-212).

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