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Understanding Electrical Line Resistance At Advanced Semiconductor Nodes

Exploring the impact of process variation on DRAM wordline resistance.

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When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by grain boundary effects and surface scattering. Consequently, resistivity varies throughout a line, and resistance extraction needs to account for these secondary phenomena for improved resistance accuracy.

Metal resistivity at different geometries is associated with feature size ([1], [2]), with a typical relationship shown in figure 1(a). So, one approach for resistance modeling is to set resistivity as a function of line width, based on empirical data. The results of this resistivity estimation on ideal structures can be seen in figure 1b; the center of the thick wire displays a resistivity approaching bulk value, whereas the thin wire has a high resistivity throughout.


Fig. 1: (a) Resistivity vs line width relationship. (b) Cross-sections showing the resistivity within wires of different dimensions. Bulk resistivity is achieved near the center of a thick wire, whereas resistivity is higher throughout a thin wire.

As a demonstration of resistance modeling, a DRAM buried wordline is modeled and its resistance extracted using the built-in capabilities of SEMulator3D. The wordline has characteristic bumps on its underside from spanning a series of saddle-fin transistors (figure 2), with wedge-shaped bottom regions between “saddles”. Due to this irregular shape, geometric-based resistivity has a significant impact on a narrow wordline’s resistance values (figure 3). The resistivities along a wordline cross-section reveal near-bulk resistivity in the center, and higher resistivity at the edges and bottom (figure 3c).


Fig. 2: Cutaway of buried wordline spanning saddle-fin transistors.


Fig. 3: (a) A buried wordline in isolation. (b) Cross-section showing the current density when voltage is applied across the line. (c) The local resistivities along a wordline cross-section reveal near-bulk resistivity in the center, and higher resistivity at the edges and bottom.

To explore the impact of process variation on DRAM wordline resistance, a study with 200 virtual fabrication cycles was then completed using Monte Carlo simulation methods in SEMulator3D. This experiment was conducted to identify important process parameters that affect electrical resistance. Based on a linear regression analysis, significant parameters that affect electrical resistance were identified as silicon etch selectivity, mandrel etch lateral ratio, high-k dielectric thickness, and silicon etch when forming the active area (figure 4). Using the results of this sensitivity analysis, process changes could be initiated to optimize device resistance. In our example, wordline recess depth and etch selectivity (to active area silicon) have the greatest effect on wordline resistance (figure 5), and they can be adjusted until a targeted wordline resistance is achieved.


Fig. 4: Linear regression model for wordline resistance.


Fig. 5: Sensitivity analysis for wordline module enables process tuning to reach resistance target.

Understanding the relationship between resistivity and device geometry is important when calculating resistance for varying metal structures with small linewidths. This understanding is critical when extracting the resistance of challenging geometries, such as those found in DRAM wordlines. Using accurate resistance extraction techniques and virtual variation studies, process parameters can be optimized to meet electrical resistance targets for DRAM devices and other advanced technologies.

References:

  1. Josell, Daniel, Sywert H. Brongersma, and Zsolt Tőkei. “Size-Dependent Resistivity in Nanoscale Interconnects.” Annual Review of Materials Research 39, no. 1 (August 2009): 231–54.
  2. G Steinlesberger, M Engelhardt, G Schindler, J Kretz, W Steinhögl, E Bertagnolli, “Processing technology for the investigation of sub-50 nm copper damascene interconnects”, Solid-State Electronics, Vol. 47, Issue 7, 2003, Pages 1237-1241.


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