Avoiding Gloom With Better Knowledge


The rate of product development is facing very real challenges as the pace of silicon technology evolution begins to slow. Today, we are squeezing the most out of transistor physics, which is essentially derived from 60-year-old CMOS technology. To maintain the pace of Moore’s law, it is predicted that in 2030 we will need transistors to be a sixth of their current size. Reducing transistor s... » read more

Wrestling With Variation In Advanced Node Designs


Variation is becoming a major headache at advanced nodes, and issues that used to be dealt with in the fab now must be dealt with on the design side, as well. What is fundamentally changing is that margin, which has long been used as a buffer for variation and other manufacturing process-related problems, no longer works in these leading-edge designs for a couple of reasons. First, margin im... » read more

Analog Simulation At 7/5/3nm


Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Interdependencies Complicate IC Power Grid Design


Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of... » read more

A Study Of Next-Generation CFET Process Integration Options


Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process m... » read more

Making Random Variation Less Random


The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations


By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Effects Of A Random Process Variation On The Transfer Characteristics Of A Fundamental Photonic Integrated Circuit Component


Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Node Within A Node


Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

Controlling Variability And Cost At 3nm And Beyond


Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

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