tag: process variation

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill
By HJ Kim - 21 May, 2026 - Comments: 0

As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication
By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

Understanding Within-Wafer Variations: A Virtual Fabrication Approach
By Sam Sarkar - 19 Feb, 2026 - Comments: 0

One of the unavoidable aspects of chip manufacturing is that some dies on a wafer perform differently than others, even though they were made together on the same wafer. This blog dives into that mystery and provides a way to predict and fix these issues. Imagine baking cookies. If your oven has hot and cold spots, some cookies will be perfect; others burnt. That’s what happens in chip man... » read more

Overcoming BEOL Patterning Challenges At The 3nm Node
By Assawer Soussou - 20 Nov, 2025 - Comments: 0

As complementary metal-oxide semiconductor (CMOS) area shrinks 50% from one node to the next, interconnect critical dimensions (CD) and pitch (or spacing) are under tight demands. At the N3 node, where metal pitch dimensions must be at or below 18 nm,1,2 one of the main interconnect challenges is securing sufficient process margins for CD and edge placement error (EPE). Achieving the... » read more

Framework for Optimizing Reliability and Thermal Management of 3DICs (National Taiwan Univ., Lamar Univ.)
By Technical Paper Link - 10 Oct, 2025 - Comments: 0

A new technical paper titled "The Impact of Process Variations on the Thermo-Mechanical Behavior of 3D Integrated Circuits" was published by researchers at National Taiwan University and Lamar University. Abstract "The use of vertically stacked architectures in three-dimensional integrated circuits (3DICs) offers a transformative path for advancing Moore’s Law by significantly boosting co... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control
By Gregory Haley - 02 Oct, 2025 - Comments: 0

When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Tuning Design And Process For High-NA EUV Stitching
By Kevin Lucas - 24 Oct, 2024 - Comments: 0

By Kevin Lucas and James Ban Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, see figure 1. The lithography patterning at a stitching boundary between two mask exposures will be affected by additional process variation than are encountered in ... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

Challenges And Outlook Of ATE Testing For 2nm SoCs
By Sriharsha Vinjamury - 08 Aug, 2024 - Comments: 0

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

← Older posts

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy