Reducing Design Margins With Silicon Model Calibration

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

Design Flow Challenged By 3D-IC Process, Thermal Variation

3D-ICs are proving a challenge even for designers accustomed to dealing with power and performance tradeoffs, but they are considered an inevitable migration path for leading-edge designs due to the compute demands of AI and the continual shrinking of digital logic. 3D-ICs are widely viewed as the way to continue scaling beyond the limits of planar SoCs, and a way to add more heterogeneous d... » read more

Predicting And Preventing Process Drift

Increasingly tight tolerances and rigorous demands for quality are forcing chipmakers and equipment manufacturers to ferret out minor process variances, which can create significant anomalies in device behavior and render a device non-functional. In the past, many of these variances were ignored. But for a growing number of applications, that's no longer possible. Even minor fluctuations in ... » read more

What’s Missing In 2.5D EDA Tools

Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

Strategies For Detecting Sources Of Silent Data Corruption

Engineering teams are wrestling with how to identify the root causes of silent data corruption (SDC) in a timely and cost-effective way, but the solutions are turning out to be broader and more complex than simply fixing a single defect. This is particularly vexing for data center reliability, accessibility and serviceability (RAS) engineering teams, because even the best tools and methodolo... » read more

Speeding Up Design Closure

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

Impacts Of Process Flow, Scaling, And Variability On Interconnect Performance

Virtual fabrication is used to evaluate the performance of interconnects (line and via resistance, capacitance, etc.) across pitches compatible with either EUV single exposure or SADP for three different process flows: single damascene, dual damascene, and semi-damascene (subtractive metal etch). The effects of process variation for the three flows are also investigated to determine the relativ... » read more

Solving The Reliability Problem Of Memristor-Based Artificial Neural Networks

A technical paper titled "ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation" was published by researchers at Eindhoven University of Technology, University of Tehran, and USC. Abstract: "Memristor-based in-memory neuromorphic computing systems promise a highly efficient implementation of vector-matrix multiplications, commonly used in artificial neural networks (ANNs). H... » read more

Wafer-Scale Variability In Photonic Devices & Effects On Circuits

A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

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