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Wafer-Scale Variability In Photonic Devices & Effects On Circuits


A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes


In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

The Gargantuan 5G Chip Challenge


Blazing fast upload and download speeds for cellular data are coming, but making the technology function as expected throughout its expected lifetime is an enormous challenge that will require substantial changes across the entire chip ecosystem. While sub-6GHz is an evolutionary step from 4G LTE, the real promise of 5G kicks in with millimeter-wave (mmWave) technology. But these higher-freq... » read more

Understanding Electrical Line Resistance At Advanced Semiconductor Nodes


When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by grain boundary effects and surface scattering. Consequently, resistivity varies throughout a line, and resistance extraction needs to account for these secondary phenome... » read more

Robust Variation-Aware Smart Power Designs For Silicon Success


Power management ICs (PMICs) is a rapidly growing segment in the semiconductor industry. The growth has been fueled by the demand for Smart Power applications that include wearable electronics, mobile computing platforms, printers, hard disk drives (HDD), IoT devices, and the full array of automotive applications. According to a report from market research firm Coherent Market Insights, the gl... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication


A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Dealing With Sub-Threshold Variation


Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

The Challenge Of Balancing Performance And Accuracy For Advanced Node Timing Signoff


As process nodes shrink, complexity, cost and overall risk expand. Process variability that once was once acceptable now becomes a critical item as operating voltage decreases. Simply adding design margin makes the chip non-competitive. Physical effects that were once ignored now become critical as well. The impact of interconnect can no longer be modeled based on simple circuit topology. Layou... » read more

Better Analytics Needed For Assembly


Package equipment sensors, newer inspection techniques, and analytics enable quality and yield improvement, but all of those will require a bigger investment on the part of assembly houses. That's easier said than done. Assembly operations long have operated on thin profit margins because their tasks were considered easy to manage. Much has changed over the past several years, however. The r... » read more

No Two Chips Are Alike


As semiconductor processes continue to shrink it’s becoming increasingly challenging to manage the parameters of individual devices not only across the diameter of the wafer, but also across the length of a single chip, especially for a complex chip with a large area. Today’s standard approach to this problem is to assume the worst case and to create a sub-optimal design that accommodates t... » read more

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