Why 3D device simulation is essential for maximizing performance.
2-D MOSFETs have proven difficult to scale down to 20nm and beyond. In their place, 3D FinFET transistors have emerged as novel devices that can scale down to lower node sizes. 10nm process finFETs are for SoC product mass production, and research is progressing towards a 7nm process finFET. FinFET transistors provide lower dynamic power consumption (due to flatter I-V curves), improved control over short channel effects, a reduction of leakage current, superior on/off contrast, and most importantly, less wafer area per transistor than 2-D MOSFET technology.
Unfortunately, the transition from planar to finFET technology has come with new sources of variability inherent in 3D device geometry. 3D device simulation can be a very useful tool to investigate the impact of this variability on device performance. 3D simulation is widely used to analyze and optimize MOSFET characteristics such as threshold voltage, on / off current, sub-threshold swing and drain-induced barrier lowering due to changes in fin geometry, doping concentration, and other 3D device geometry variations. Furthermore, the effects of random fluctuations in process distribution and roughness can be explored using semiconductor process simulation platforms such as SEMulator3D.
To read more, click here.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Foundry forms ASIC subsidiary as it focuses on 14nm/12nm and above.
Market overcrowding, more efficient manufacturing, and growing list of scaling issues create a challenging competitive landscape.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Why auto tech companies are so concerned about interactions with humans.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply