Understanding The Effect Of Variability In Bulk FinFET Device Performance

2-D MOSFETs have proven difficult to scale down to 20nm and beyond. In their place, 3D FinFET transistors have emerged as novel devices that can scale down to lower node sizes. 10nm process finFETs are for SoC product mass production, and research is progressing towards a 7nm process finFET. FinFET transistors provide lower dynamic power consumption (due to flatter I-V curves), improved control over short channel effects, a reduction of leakage current, superior on/off contrast, and most importantly, less wafer area per transistor than 2-D MOSFET technology.

Unfortunately, the transition from planar to finFET technology has come with new sources of variability inherent in 3D device geometry. 3D device simulation can be a very useful tool to investigate the impact of this variability on device performance. 3D simulation is widely used to analyze and optimize MOSFET characteristics such as threshold voltage, on / off current, sub-threshold swing and drain-induced barrier lowering due to changes in fin geometry, doping concentration, and other 3D device geometry variations. Furthermore, the effects of random fluctuations in process distribution and roughness can be explored using semiconductor process simulation platforms such as SEMulator3D.

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