Exploring New Scaling Approaches

UC discusses implant litho, reconfigurable wires and almost gate-all-around.

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At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography 2017 conference, Semiconductor Engineering sat down to discuss semiconductor technology with Tsu-Jae King Liu, the TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. More specifically, Liu discussed some of the new and alternative approaches in chip manufacturing that are being explored at UC Berkeley. Clearly, the industry needs to consider new ideas as traditional chip scaling is slowing down and becoming more complex. Here are excerpts of that conversation.

SE: During the presentation at the conference, you talked about an alternative approach called tilted ion implantation (TII) lithography. What’s behind the thinking here?

Liu: The idea is to continue to allow the industry to define features smaller than the wavelength of light, but at reasonable costs. That is the challenge with multiple patterning. So in quadruple and octuple patterning, the challenge is that the costs are going escalate too rapidly for the industry to stay on the two-year cadence of Moore’s Law.

SE: In papers, TII lithography is described as an alternative approach to self-aligned double patterning (SADP). It can be used to scale features down to 10nm half-pitch and beyond, but it is less expensive than SADP. What is ion implantation lithography?

Liu: Tilted ion implantation is a well-established process. It can be used with existing multi-patterning techniques to further increase the density of the features. It’s to help enable the industry to scale. It can be incorporated into the SADP flow. So rather than doing SADP twice, like doing the spacers on the sidewalls of spacers, you can just use spacers and then tilted implantation to double the feature density. As the spacers come closer together, they risk the possibility of collapsing into each other, because of surface adhesive forces and capillary forces in the application process. Tilted ion implantation doesn’t have that issue. It will help to double the density of features beyond the limit of even conventional self-aligned double patterning.

SE: What type of ion implanters are required for this?

Liu: This involves a very, very low-energy and moderate dose. It’s less than 10(15) per centimeter square. For the source-drain implants, it’s usually above 10(15) per centimeter square. This is like half that dose. So, it’s medium-current implanters. It’s standard implant tools. It also uses existing materials and processes that the industry already uses today in high-volume manufacturing.

SE: For this research, it appears that UC Berkeley obtained some funding from Applied Materials and Lam Research. Is the industry looking at this?

Liu: The industry has been focusing a lot of their efforts on self-aligned double patterning, because it’s self-aligned and it gets the feature sizes down. But as they realize there are limits to self-aligned double patterning, they will need to look at complementary approaches like tilted implantation.

SE: What’s next?

Liu: What I’d like to do is to go further and do something that self-aligned double patterning cannot do. This is to go back to enabling 2D layouts. That will make a big difference for the industry. And I know EUV is the ultimate goal. But it might take a few more years to make that even manufacturable in terms of high yield and to get 2D features.

SE: Can you use ion implant litho with EUV?

Liu: Yes, certainly.

SE: During the presentation, you also talked about re-configurable interconnects for backend-of-the-line (BEOL) processes. This is where the metal layers and tiny copper interconnects are made in chips. Can you describe the work you are doing here?

Liu: With all of the layers of metal, we essentially already have a 3D structure. We have so many layers of material over the CMOS transistor. So why don’t we make better use of those stacked 3D layers of metal interconnects. That’s the idea. The key is to enhance the functionality at a reasonable cost per function. If we can make the metal interconnects more functional than they are today, and because the industry has already learned how to make air gaps, we could just leverage that trend to modify the backend-of-the-line process to enable some of the interconnects to be re-configured. It actually turns out to be much more energy efficient.

SE: How does this work?

Liu: Let me explain. Within a field-programmable gate array device, you can reprogram it. But the functionality of an FPGA is determined by some configuration memory. So first of all, you have to load the configuration of the interconnects from a nonvolatile memory chip onto your FPGA. So you load that information into SRAM. So basically, to re-configure an interconnect in an FPGA, you need a transistor to make an interconnection or not. The state of that transistor is determined by the SRAM cell, which you program. So, you need six transistors to make a connection. If you allow the wires to move, you can eliminate the need for those extra transistors to determine how to interconnect the wires. You just physically change the connection of the wires themselves.

SE: What else?

Liu: You leverage the lower layers of metal to form the actuation electrons. You have five or six layers. You can implement an actuation electrode. You apply a voltage and it electrostatically attracts the metal wires one way or another. So you can dynamically with very low energy re-configure your key interconnections in your chip. This is a new capability for future chips. It’s along the vain of 3D integration.

SE: I’ve also noticed that you’ve conducted research on nano-electro-mechanical (NEM) and MEMS relay devices. The idea is to create a mechanical switch, right?

Liu: Some of the work I’ve done is really aimed to use all mechanical devices for computing. Only a mechanical switch can really achieve a very low operating voltage. We are aiming for 10 millivolts. No matter what transistor you make, it can’t operate at 10 millivolts over a wide range of temperatures with zero off-state current and good on-state current. For certain applications like the Internet of Things, mechanical switches should be compelling.

SE: Last year, Lawrence Berkeley National Laboratory devised a transistor with a working 1nm gate. The key was to use carbon nanotubes and molybdenum disulfide (MoS2). Researchers devised a MoS2 transistor with the carbon-nanotube gate, right?

Liu: That was a proof-of-concept. The challenge for these transition-metal dichalcogenide materials is how do you form them over these 300mm wafers with good uniformity. Right now, they are best grown on some substrate and transferred to silicon. It’s not clear if that will be cost effective. But that’s for engineers to investigate.

Schematic of a transistor with a molybdenum disulfide channel and 1-nanometer carbon nanotube gate. (Credit: Sujay Desai/UC Berkeley)

SE: Clearly, finFETs will scale to 7nm and perhaps to 5nm. Then, the industry is working on nanowire FETs or gate-all-around FETs for the next nodes. Are you bullish about nanowire FETs?

Liu: Yes. I have also been publishing an alternative approach, where it’s not quite gate-all-around. It’s almost all around. It’s easier to manufacture. I have some publications, where we describe a way to evolve the finFET with tall and narrow fins into a structure with some layers of oxide inserted in the fins. Imagine if you have a fin with some layers of oxide inserted periodically. What those oxide layers do is they allow electro fields to come from the gate into the channel region to help enhance gate control. The key for transistor scaling is to enhance gate control.

SE: So it’s not exactly a gate-all-around device, right?

Liu: I am actually proposing kind of like a nanowire shape, but you don’t need to wrap the gate physically all around it. You just need to give the gate access through some oxide to be able to have fringing electric fields to penetrate into the channels to enhance gate control.

SE: There is a lot of talk about the slowdown in transistor scaling. Any thoughts here?

Liu: We are a long way from fundamental physical limits of transistor miniaturization.



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