tag: GAA FET

Scaling of 2D Semiconductor Nanoribbons for High Performance Transistors (Purdue, NUS et al.)
By Technical Paper Link - 21 Jan, 2026 - Comments: 0

A new technical paper titled "Scaling of Two-Dimensional Semiconductor Nanoribbons for High-Performance Electronics" was published by researchers at Purdue University, National University of Singapore, Nexstrom Pte. Ltd and Dankook University. Abstract "Monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs), with their atomically thin bodies, are promising candida... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips
By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control
By Jiangtao Hu - 09 Dec, 2025 - Comments: 0

AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, manufacturers are rapidly accelerating advanced logic and DRAM development. Chief among these innovations: gate-all-around (GAA) logic transistor and vertical gate (VG) DRAM, two device architectures that promise higher performance, improved power efficiency, and greater scalabil... » read more

Research Bits: June 9
By Jesse Allen - 09 Jun, 2025 - Comments: 0

InGaOx GAA transistor Researchers from the University of Tokyo created a gate-all-around transistor made from gallium-doped indium oxide (InGaOx). Doping indium oxide with gallium suppressed oxygen vacancies, improving transistor reliability. "We wanted our crystalline oxide transistor to feature a 'gate-all-around' structure, whereby the gate, which turns the current on or off, surrounds t... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks
By Sam Sarkar - 17 Apr, 2025 - Comments: 0

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

Research Bits: Mar. 25
By Jesse Allen - 25 Mar, 2025 - Comments: 0

2D materials in 3D transistors Researchers at the University of California Santa Barbara investigated 3D gate-all-around (GAA) transistors made using 2D semiconductors. They considered three different approaches to channel stacking: nano-sheet FETs, nano-fork FETs, and nano-plate FETs. The nano-plate FET architecture, which exploits lateral stacking of 2D layers, was found to maximize the g... » read more

Mechanical Stress In Semiconductor Development
By Ivan Chakarov - 20 Feb, 2025 - Comments: 0

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,1 mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property de... » read more

TCAD Simulation Challenges For Gate-All-Around Transistors
By Victor Moroz - 17 Dec, 2024 - Comments: 0

By Victor Moroz and Shela Aboud The transition from finFET technology to Gate-All-Around (GAA) technology helps to reduce transistor variability and resume channel length scaling. It also brings several new challenges in terms of transistor design that need to be addressed. One of the challenges is handling the thin Si layers that come with GAA technology, where Si channel thickness scale... » read more

Challenges And Outlook Of ATE Testing For 2nm SoCs
By Sriharsha Vinjamury - 08 Aug, 2024 - Comments: 0

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

Understanding CFETs, A Next Generation Transistor Architecture
By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

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