Intel Vs. Samsung Vs. TSMC

By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

How To Get The Most Out Of Gate-All-Around Designs

By Andrew Appleby - 25 Apr, 2024 - Comments: 0

The semiconductor industry has relied on finFETs, three-dimensional field-effect transistors with thin vertical fins, for many generations of technology. However, the industry is reaching the limits of how much finFETs can be shrunk while maintaining their speed and power benefits, which are crucial for artificial intelligence (AI) and machine learning (ML) applications. The solution is the gat... » read more

TSMC Uncorks A16 With Super Power Rail

By Barry Pangrle - 25 Apr, 2024 - Comments: 0

TSMC showed off its forthcoming A16 process technology node, targeted for the second half of 2026, at its 30th North American Technology Symposium this week. As the foundry moves from nanometer to angstrom process numbering, the new nodes will be prefixed with an “A” designation (instead of “N”) and A16 is the first for TSMC. TSMC said that N2 is still tracking to a 2025 production s... » read more

Unlocking PPA Benefits of Backside Routing

By Synopsys - 10 Apr, 2024 - Comments: 0

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

Powering CFETs From The Backside

By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Backside Power Delivery Adds New Thermal Concerns

By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

The Rising Price Of Power In Chips

By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

Thinking Big: From Chips To Systems

By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

Backside Power Delivery Gears Up For 2nm Devices

By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

Big Changes Ahead In Power Delivery, Materials, And Interconnects

By Laura Peters - 22 Mar, 2023 - Comments: 0

Part one of this forecast looked at evolving transistor architectures and lithography platforms. This report examines revolutions in interconnects and packaging. When it comes to device interconnects, it’s hard to beat copper. Its low resistivity and high reliability have served the industry exceedingly well as both on-chip interconnect and wires between chips. But in logic chips, with int... » read more

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