tag: backside power delivery

Extraction Challenges of CFET and Backside Power Delivery
By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips
By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Reliability Risks Shift To The Materials Stack
By Gregory Haley - 18 Dec, 2025 - Comments: 0

The semiconductor industry’s push into 3D integration and large-format substrates has fundamentally changed the role of materials in packaging. What were once structural supports and electrical insulators have become critical performance limiters. Modern packages contain far more polymers, adhesives, advanced dielectrics, thermal materials, and composite laminates than previous generations... » read more

Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)
By Technical Paper Link - 17 Oct, 2025 - Comments: 0

A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

Wafer Warpage Evolution During Key Backside Power Delivery Network Fabrication Steps (Korea Univ., Georgia Tech)
By Technical Paper Link - 08 Oct, 2025 - Comments: 0

A new technical paper titled "Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication" was published by researchers at Korea University and Georgia Institute of Technology. Abstract "As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs),... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era
By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Novel Assembly Approaches For 3D Device Stacks
By Laura Peters - 30 Jun, 2025 - Comments: 0

The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Power Delivery Challenges For AI Chips
By Gregory Haley - 19 Jun, 2025 - Comments: 0

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

Determinants Of Bond Wave Speed In Wafer Bonding (Yokohama, TEL)
By Technical Paper Link - 05 Jun, 2025 - Comments: 0

A recent technical paper titled "Factors determining bond wave speed in wafer bonding" was published by researcher at Yokohama National University, Tokyo Electron Kyushu Limited and ANVOS Analytics. Abstract "Wafer-level direct bonding has become a critical process for advanced 3D architectures in logic, memory, and CMOS image sensors. The minimization of the wafer distortion caused by wafe... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks
By Sam Sarkar - 17 Apr, 2025 - Comments: 0

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

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