More Performance At The Edge


Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

The Race To Accelerate


Geoff Tate, CEO of [getentity id="22921" e_name="Flex Logix"], sat down with Semiconductor Engineering to discuss how the chip industry is changing, why that bodes well for embedded FPGAs, and what you need to be aware of when using programmable logic on the same die as other devices. What follows are excerpts of that conversation. SE: What are the biggest challenges facing the chip industry... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications


With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

New Drivers For I/O


Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Performance Increasingly Tied To I/O


Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

How Many Cores? (Part 1)


The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

Neuromorphic Chip Biz Heats Up


It’s no secret that today’s computers are struggling to keep up with the enormous demands of data processing and bandwidth, and the whole electronics industry is searching for new ways to enable that. The traditional approach is to continue to push the limits of today’s systems and chips. Another way is to go down the non-traditional route, including an old idea that is generating stea... » read more

Tackling RF Desense Challenges At The Source


Just imagine you are stepping out of the electronics store with your brand new smart phone. You eagerly scroll down your contacts to dial your best friend and proudly tell them the great news, but as soon as they pick up, your reception is gone! What happened? This problem is commonly described as desense, a degradation of the sensitivity of the receiver due to external noise sources. Desens... » read more

PCI Express 4.0 Controller Design And Integration Challenges


Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers. Outline Markets & Applications fo... » read more

Programmable Risk Factors


The semiconductor industry is starting to come around to the realization that security begins at the block level. Intellectual property (IP) is being seen with IP blocks that can be woven into the general-purpose system-on-chip (SoC) hardware layers to secure I/O, data, keys, and various other sensitive or critical information. But modifying hardware designs in response to the demands placed... » read more

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