Performance Increasingly Tied To I/O

Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

How Many Cores? (Part 1)

The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

Neuromorphic Chip Biz Heats Up

It’s no secret that today’s computers are struggling to keep up with the enormous demands of data processing and bandwidth, and the whole electronics industry is searching for new ways to enable that. The traditional approach is to continue to push the limits of today’s systems and chips. Another way is to go down the non-traditional route, including an old idea that is generating stea... » read more

Tackling RF Desense Challenges At The Source

Just imagine you are stepping out of the electronics store with your brand new smart phone. You eagerly scroll down your contacts to dial your best friend and proudly tell them the great news, but as soon as they pick up, your reception is gone! What happened? This problem is commonly described as desense, a degradation of the sensitivity of the receiver due to external noise sources. Desens... » read more

PCI Express 4.0 Controller Design And Integration Challenges

Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers. Outline Markets & Applications fo... » read more

Programmable Risk Factors

The semiconductor industry is starting to come around to the realization that security begins at the block level. Intellectual property (IP) is being seen with IP blocks that can be woven into the general-purpose system-on-chip (SoC) hardware layers to secure I/O, data, keys, and various other sensitive or critical information. But modifying hardware designs in response to the demands placed... » read more

Tech Talk: Silicon Photonics

Mentor Graphics' John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the first part in a two-part series. [youtube vid=0ydkDmrSrF4] » read more

Managing Electrical Communications Better

By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

The Deafening Problem Of High-Speed I/O

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more